Thyristor-based volatile memory in nano-scale CMOS

Rich Roy, Farid Nemati, Ken Young, Bruce Bateman, Rajesh Chopra, Seong Ook Jung, Chiming Show, Hyun Jin Cho

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)


A thyristor-based memory cell technology provides SRAM-like performance at 2× to 3× the density of conventional 6T SRAM. The technology is readily embedded into conventional nano-scale CMOS and scales into future SOI and FinFET technologies. A 19mm2 0.13μm 9Mb SOI test chip has a 0.562μm2 cell with a cell-RAV time <2ns.

Original languageEnglish
Title of host publication2006 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers
Publication statusPublished - 2006
Event2006 IEEE International Solid-State Circuits Conference, ISSCC - San Francisco, CA, United States
Duration: 2006 Feb 62006 Feb 9

Publication series

NameDigest of Technical Papers - IEEE International Solid-State Circuits Conference
ISSN (Print)0193-6530


Other2006 IEEE International Solid-State Circuits Conference, ISSCC
Country/TerritoryUnited States
CitySan Francisco, CA

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering


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