Thyristor-based volatile memory in nano-scale CMOS

Rich Roy; Farid Nemati; Ken Young; Bruce Bateman; Rajesh Chopra; Seong Ook Jung; Chiming Show; Hyun Jin Cho

Thyristor-based volatile memory in nano-scale CMOS

Rich Roy, Farid Nemati, Ken Young, Bruce Bateman, Rajesh Chopra, Seong Ook Jung, Chiming Show, Hyun Jin Cho

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Citations (Scopus)

Abstract

A thyristor-based memory cell technology provides SRAM-like performance at 2× to 3× the density of conventional 6T SRAM. The technology is readily embedded into conventional nano-scale CMOS and scales into future SOI and FinFET technologies. A 19mm² 0.13μm 9Mb SOI test chip has a 0.562μm² cell with a cell-RAV time <2ns.

Original language	English
Title of host publication	2006 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers
Pages	632+621
Publication status	Published - 2006
Event	2006 IEEE International Solid-State Circuits Conference, ISSCC - San Francisco, CA, United States Duration: 2006 Feb 6 → 2006 Feb 9

Publication series

Name	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
ISSN (Print)	0193-6530

Other

Other	2006 IEEE International Solid-State Circuits Conference, ISSCC
Country/Territory	United States
City	San Francisco, CA
Period	06/2/6 → 06/2/9

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Cite this

@inproceedings{db9fa28db02c4067944aaa0f14ddc1d8,

title = "Thyristor-based volatile memory in nano-scale CMOS",

abstract = "A thyristor-based memory cell technology provides SRAM-like performance at 2× to 3× the density of conventional 6T SRAM. The technology is readily embedded into conventional nano-scale CMOS and scales into future SOI and FinFET technologies. A 19mm2 0.13μm 9Mb SOI test chip has a 0.562μm2 cell with a cell-RAV time <2ns.",

author = "Rich Roy and Farid Nemati and Ken Young and Bruce Bateman and Rajesh Chopra and Jung, {Seong Ook} and Chiming Show and Cho, {Hyun Jin}",

year = "2006",

language = "English",

isbn = "1424400791",

series = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference",

pages = "632+621",

booktitle = "2006 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers",

note = "2006 IEEE International Solid-State Circuits Conference, ISSCC ; Conference date: 06-02-2006 Through 09-02-2006",

}

Roy, R, Nemati, F, Young, K, Bateman, B, Chopra, R, Jung, SO, Show, C & Cho, HJ 2006, Thyristor-based volatile memory in nano-scale CMOS. in 2006 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers., 1696327, Digest of Technical Papers - IEEE International Solid-State Circuits Conference, pp. 632+621, 2006 IEEE International Solid-State Circuits Conference, ISSCC, San Francisco, CA, United States, 06/2/6.

Thyristor-based volatile memory in nano-scale CMOS. / Roy, Rich; Nemati, Farid; Young, Ken et al.

2006 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers. 2006. p. 632+621 1696327 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Thyristor-based volatile memory in nano-scale CMOS

AU - Roy, Rich

AU - Nemati, Farid

AU - Young, Ken

AU - Bateman, Bruce

AU - Chopra, Rajesh

AU - Jung, Seong Ook

AU - Show, Chiming

AU - Cho, Hyun Jin

PY - 2006

Y1 - 2006

N2 - A thyristor-based memory cell technology provides SRAM-like performance at 2× to 3× the density of conventional 6T SRAM. The technology is readily embedded into conventional nano-scale CMOS and scales into future SOI and FinFET technologies. A 19mm2 0.13μm 9Mb SOI test chip has a 0.562μm2 cell with a cell-RAV time <2ns.

AB - A thyristor-based memory cell technology provides SRAM-like performance at 2× to 3× the density of conventional 6T SRAM. The technology is readily embedded into conventional nano-scale CMOS and scales into future SOI and FinFET technologies. A 19mm2 0.13μm 9Mb SOI test chip has a 0.562μm2 cell with a cell-RAV time <2ns.

UR - http://www.scopus.com/inward/record.url?scp=39749187678&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=39749187678&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:39749187678

SN - 1424400791

SN - 9781424400799

T3 - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

SP - 632+621

BT - 2006 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers

T2 - 2006 IEEE International Solid-State Circuits Conference, ISSCC

Y2 - 6 February 2006 through 9 February 2006

ER -

Thyristor-based volatile memory in nano-scale CMOS

Abstract

Publication series

Other

All Science Journal Classification (ASJC) codes

Other files and links

Fingerprint

Cite this