Thyristor-based volatile memory in nano-scale CMOS

Rich Roy, Farid Nemati, Ken Young, Bruce Bateman, Rajesh Chopra, Seong Ook Jung, Chiming Show, Hyun Jin Cho

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

A thyristor-based memory cell technology provides SRAM-like performance at 2× to 3× the density of conventional 6T SRAM. The technology is readily embedded into conventional nano-scale CMOS and scales into future SOI and FinFET technologies. A 19mm2 0.13μm 9Mb SOI test chip has a 0.562μm2 cell with a cell-RAV time <2ns.

Original languageEnglish
Title of host publication2006 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers
Pages632+621
Publication statusPublished - 2006 Dec 1
Event2006 IEEE International Solid-State Circuits Conference, ISSCC - San Francisco, CA, United States
Duration: 2006 Feb 62006 Feb 9

Publication series

NameDigest of Technical Papers - IEEE International Solid-State Circuits Conference
ISSN (Print)0193-6530

Other

Other2006 IEEE International Solid-State Circuits Conference, ISSCC
CountryUnited States
CitySan Francisco, CA
Period06/2/606/2/9

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'Thyristor-based volatile memory in nano-scale CMOS'. Together they form a unique fingerprint.

  • Cite this

    Roy, R., Nemati, F., Young, K., Bateman, B., Chopra, R., Jung, S. O., Show, C., & Cho, H. J. (2006). Thyristor-based volatile memory in nano-scale CMOS. In 2006 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers (pp. 632+621). [1696327] (Digest of Technical Papers - IEEE International Solid-State Circuits Conference).