Digital circuits can be implemented based on highly complex non-periodic clocking schemes. However, the conventional timing verifiers do not guarantee the correctness of timing analysis because they cannot consider full timing behaviors of a gated clock. This paper describes a novel hybrid timing verification approach which handles circuits using non-periodic gated clocking schemes. For its non-periodic nature of the gated clock, timing constraints must be generated with considering full behaviors of the gated clock. Experimental results show that the proposed technique performs more complete and more reliable timing verification than conventional timing verifiers.
|Number of pages||4|
|Journal||Proceedings - IEEE International Symposium on Circuits and Systems|
|Publication status||Published - 1996 Jan 1|
|Event||Proceedings of the 1996 IEEE International Symposium on Circuits and Systems, ISCAS. Part 1 (of 4) - Atlanta, GA, USA|
Duration: 1996 May 12 → 1996 May 15
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering