DRAM refresh power, which is consumed solely to preserve data, is rapidly increasing as capacity increases. A study predicts that the power will account for up to 35% of total DRAM power in the high capacity DRAM device. While various schemes were proposed to reduce the refresh power, those could not be adopted to commercial products due to cost overhead and design complexity issues. In this paper, we propose a simple refresh power saving scheme called TWW. We implement it with a much smaller amount of register size than previous works without modification on OS and DRAM controller. It eliminates unnecessary refresh operation of pre-activated rows in a specific timing window with optimum register size. We can save the refresh power up to 16% with only 6.2 KB registers in a DRAM device. This paper explains the implementation of the proposed scheme and shows the power saving effectiveness with gem5 full system simulator.
|Title of host publication||2017 22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Number of pages||6|
|Publication status||Published - 2017 Feb 16|
|Event||22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017 - Chiba, Japan|
Duration: 2017 Jan 16 → 2017 Jan 19
|Name||Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC|
|Other||22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017|
|Period||17/1/16 → 17/1/19|
Bibliographical noteFunding Information:
This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIP) (2016R1A2B4011799), by the IDEC and by Samsung Electronics.
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
- Computer Science Applications
- Computer Graphics and Computer-Aided Design