Titanium salicide process suitable for submicron CMOS applications

C. Blair; E. Demirlioglu; E. Yoon; J. Pierce

Titanium salicide process suitable for submicron CMOS applications

C. Blair, E. Demirlioglu, E. Yoon, J. Pierce

Yonsei Advanced Science Institute

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

9 Citations (Scopus)

Abstract

This paper reports a titanium salicide process capable of fabricating low resistance salicide (<5 ohms/sq.) on narrow polysilicon leads (line widths less than 0.35 μm) which are heavily doped with arsenic and boron. The process utilizes conventional processing but avoids excessive vertical scaling of the titanium silicide film. The process has been demonstrated on a 0.35 μm CMOS technology and results show that a process window exists which is suitable for technologies of 0.35 μm and below. The most serious scaling issue for titanium salicide appears to be the silicide film thickness.

Original language	English
Title of host publication	Silicides, Germanides, and Their Interfaces
Editors	Robert W. Fathauer, Siegfried Mantl, Leo J. Schowalter, K.N. Tu
Publisher	Publ by Materials Research Society
Pages	53-58
Number of pages	6
ISBN (Print)	1558992197
Publication status	Published - 1994
Event	Proceedings of the 1993 Fall Meeting of the Materials Research Society - Boston, MA, USA Duration: 1993 Nov 29 → 1993 Dec 2

Publication series

Name	Materials Research Society Symposium Proceedings
Volume	320
ISSN (Print)	0272-9172

Other

Other	Proceedings of the 1993 Fall Meeting of the Materials Research Society
City	Boston, MA, USA
Period	93/11/29 → 93/12/2

All Science Journal Classification (ASJC) codes

Materials Science(all)
Condensed Matter Physics
Mechanics of Materials
Mechanical Engineering

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Cite this

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title = "Titanium salicide process suitable for submicron CMOS applications",

abstract = "This paper reports a titanium salicide process capable of fabricating low resistance salicide (<5 ohms/sq.) on narrow polysilicon leads (line widths less than 0.35 μm) which are heavily doped with arsenic and boron. The process utilizes conventional processing but avoids excessive vertical scaling of the titanium silicide film. The process has been demonstrated on a 0.35 μm CMOS technology and results show that a process window exists which is suitable for technologies of 0.35 μm and below. The most serious scaling issue for titanium salicide appears to be the silicide film thickness.",

author = "C. Blair and E. Demirlioglu and E. Yoon and J. Pierce",

year = "1994",

language = "English",

isbn = "1558992197",

series = "Materials Research Society Symposium Proceedings",

publisher = "Publ by Materials Research Society",

pages = "53--58",

editor = "Fathauer, {Robert W.} and Siegfried Mantl and Schowalter, {Leo J.} and K.N. Tu",

booktitle = "Silicides, Germanides, and Their Interfaces",

}

Blair, C, Demirlioglu, E, Yoon, E & Pierce, J 1994, Titanium salicide process suitable for submicron CMOS applications. in RW Fathauer, S Mantl, LJ Schowalter & KN Tu (eds), Silicides, Germanides, and Their Interfaces. Materials Research Society Symposium Proceedings, vol. 320, Publ by Materials Research Society, pp. 53-58, Proceedings of the 1993 Fall Meeting of the Materials Research Society, Boston, MA, USA, 93/11/29.

Titanium salicide process suitable for submicron CMOS applications. / Blair, C.; Demirlioglu, E.; Yoon, E.; Pierce, J.

Silicides, Germanides, and Their Interfaces. ed. / Robert W. Fathauer; Siegfried Mantl; Leo J. Schowalter; K.N. Tu. Publ by Materials Research Society, 1994. p. 53-58 (Materials Research Society Symposium Proceedings; Vol. 320).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Titanium salicide process suitable for submicron CMOS applications

AU - Blair, C.

AU - Demirlioglu, E.

AU - Yoon, E.

AU - Pierce, J.

PY - 1994

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N2 - This paper reports a titanium salicide process capable of fabricating low resistance salicide (<5 ohms/sq.) on narrow polysilicon leads (line widths less than 0.35 μm) which are heavily doped with arsenic and boron. The process utilizes conventional processing but avoids excessive vertical scaling of the titanium silicide film. The process has been demonstrated on a 0.35 μm CMOS technology and results show that a process window exists which is suitable for technologies of 0.35 μm and below. The most serious scaling issue for titanium salicide appears to be the silicide film thickness.

AB - This paper reports a titanium salicide process capable of fabricating low resistance salicide (<5 ohms/sq.) on narrow polysilicon leads (line widths less than 0.35 μm) which are heavily doped with arsenic and boron. The process utilizes conventional processing but avoids excessive vertical scaling of the titanium silicide film. The process has been demonstrated on a 0.35 μm CMOS technology and results show that a process window exists which is suitable for technologies of 0.35 μm and below. The most serious scaling issue for titanium salicide appears to be the silicide film thickness.

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BT - Silicides, Germanides, and Their Interfaces

A2 - Fathauer, Robert W.

A2 - Mantl, Siegfried

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T2 - Proceedings of the 1993 Fall Meeting of the Materials Research Society

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