Titanium salicide process suitable for submicron CMOS applications

C. Blair, E. Demirlioglu, E. Yoon, J. Pierce

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Citations (Scopus)

Abstract

This paper reports a titanium salicide process capable of fabricating low resistance salicide (<5 ohms/sq.) on narrow polysilicon leads (line widths less than 0.35 μm) which are heavily doped with arsenic and boron. The process utilizes conventional processing but avoids excessive vertical scaling of the titanium silicide film. The process has been demonstrated on a 0.35 μm CMOS technology and results show that a process window exists which is suitable for technologies of 0.35 μm and below. The most serious scaling issue for titanium salicide appears to be the silicide film thickness.

Original languageEnglish
Title of host publicationSilicides, Germanides, and Their Interfaces
EditorsRobert W. Fathauer, Siegfried Mantl, Leo J. Schowalter, K.N. Tu
PublisherPubl by Materials Research Society
Pages53-58
Number of pages6
ISBN (Print)1558992197
Publication statusPublished - 1994 Jan 1
EventProceedings of the 1993 Fall Meeting of the Materials Research Society - Boston, MA, USA
Duration: 1993 Nov 291993 Dec 2

Publication series

NameMaterials Research Society Symposium Proceedings
Volume320
ISSN (Print)0272-9172

Other

OtherProceedings of the 1993 Fall Meeting of the Materials Research Society
CityBoston, MA, USA
Period93/11/2993/12/2

Fingerprint

Titanium
CMOS
titanium
Boron
Arsenic
Polysilicon
Linewidth
Film thickness
scaling
low resistance
arsenic
boron
film thickness
Processing
titanium silicide

All Science Journal Classification (ASJC) codes

  • Materials Science(all)
  • Condensed Matter Physics
  • Mechanics of Materials
  • Mechanical Engineering

Cite this

Blair, C., Demirlioglu, E., Yoon, E., & Pierce, J. (1994). Titanium salicide process suitable for submicron CMOS applications. In R. W. Fathauer, S. Mantl, L. J. Schowalter, & K. N. Tu (Eds.), Silicides, Germanides, and Their Interfaces (pp. 53-58). (Materials Research Society Symposium Proceedings; Vol. 320). Publ by Materials Research Society.
Blair, C. ; Demirlioglu, E. ; Yoon, E. ; Pierce, J. / Titanium salicide process suitable for submicron CMOS applications. Silicides, Germanides, and Their Interfaces. editor / Robert W. Fathauer ; Siegfried Mantl ; Leo J. Schowalter ; K.N. Tu. Publ by Materials Research Society, 1994. pp. 53-58 (Materials Research Society Symposium Proceedings).
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Blair, C, Demirlioglu, E, Yoon, E & Pierce, J 1994, Titanium salicide process suitable for submicron CMOS applications. in RW Fathauer, S Mantl, LJ Schowalter & KN Tu (eds), Silicides, Germanides, and Their Interfaces. Materials Research Society Symposium Proceedings, vol. 320, Publ by Materials Research Society, pp. 53-58, Proceedings of the 1993 Fall Meeting of the Materials Research Society, Boston, MA, USA, 93/11/29.

Titanium salicide process suitable for submicron CMOS applications. / Blair, C.; Demirlioglu, E.; Yoon, E.; Pierce, J.

Silicides, Germanides, and Their Interfaces. ed. / Robert W. Fathauer; Siegfried Mantl; Leo J. Schowalter; K.N. Tu. Publ by Materials Research Society, 1994. p. 53-58 (Materials Research Society Symposium Proceedings; Vol. 320).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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N2 - This paper reports a titanium salicide process capable of fabricating low resistance salicide (<5 ohms/sq.) on narrow polysilicon leads (line widths less than 0.35 μm) which are heavily doped with arsenic and boron. The process utilizes conventional processing but avoids excessive vertical scaling of the titanium silicide film. The process has been demonstrated on a 0.35 μm CMOS technology and results show that a process window exists which is suitable for technologies of 0.35 μm and below. The most serious scaling issue for titanium salicide appears to be the silicide film thickness.

AB - This paper reports a titanium salicide process capable of fabricating low resistance salicide (<5 ohms/sq.) on narrow polysilicon leads (line widths less than 0.35 μm) which are heavily doped with arsenic and boron. The process utilizes conventional processing but avoids excessive vertical scaling of the titanium silicide film. The process has been demonstrated on a 0.35 μm CMOS technology and results show that a process window exists which is suitable for technologies of 0.35 μm and below. The most serious scaling issue for titanium salicide appears to be the silicide film thickness.

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Blair C, Demirlioglu E, Yoon E, Pierce J. Titanium salicide process suitable for submicron CMOS applications. In Fathauer RW, Mantl S, Schowalter LJ, Tu KN, editors, Silicides, Germanides, and Their Interfaces. Publ by Materials Research Society. 1994. p. 53-58. (Materials Research Society Symposium Proceedings).