Topology synthesis of cascaded crossbar switches

Minje Jun, Sungjoo Yoo, Eui Young Chung

Research output: Contribution to journalArticle

11 Citations (Scopus)

Abstract

Performance requirements of on-chip network increase as system-on-chips (SoCs) are becoming more and more complex. For high-performance applications, crossbar switch-based networks are replacing the traditional shared buses as the backbone networks in SoCs. In this paper, we tackle the topology design of on-chip networks with crossbar switches in a cascaded fashion. We also resolve the unacceptable complexity of our previous method based on mixed integer linear programming by a heuristic method. Experimental results show that the proposed method overcomes the frequency limitation of the single crossbar-based design, particularly when the wire delay effect is considered. The proposed heuristic method also achieves more area reduction (up to 69.5%) over the existing methods, and finds as good solutions as the exact method while the synthesis time is saved by orders of magnitude.

Original languageEnglish
Article number4957604
Pages (from-to)926-930
Number of pages5
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume28
Issue number6
DOIs
Publication statusPublished - 2009 Jun 1

Fingerprint

Heuristic methods
Switches
Topology
Linear programming
Wire
Network-on-chip
System-on-chip

All Science Journal Classification (ASJC) codes

  • Software
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

Cite this

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Topology synthesis of cascaded crossbar switches. / Jun, Minje; Yoo, Sungjoo; Chung, Eui Young.

In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 28, No. 6, 4957604, 01.06.2009, p. 926-930.

Research output: Contribution to journalArticle

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