Toward 1024-channel parallel neural recording: Modular Δ-ΔΣ Analog front-end architecture with 4.84fJ/C-s·mm2 energy-area product

Sung Yun Park; Jihyun Cho; Kyounghwan Na; Euisik Yoon

doi:10.1109/VLSIC.2015.7231344

Toward 1024-channel parallel neural recording: Modular Δ-ΔΣ Analog front-end architecture with 4.84fJ/C-s·mm² energy-area product

Sung Yun Park, Jihyun Cho, Kyounghwan Na, Euisik Yoon

Yonsei Advanced Science Institute

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

15 Citations (Scopus)

Abstract

We report an energy- and area-efficient modular analog front-end (AFE) architecture incorporating Δ-modulated ΔΣ (Δ-ΔΣ) signal acquisition for 1,024-channel brain activity monitoring platforms. The AFE employs spectrum-equalizing and continuous-time (CT)-ΔΣ quantization to make use of the inherent spectral characteristics of brain signals. The dynamic range (DR) of the neural signals has been compressed by 27dB (spectrum equalization). The energy-area product is the most critical figure of merit for massively-parallel recordings and the AFE achieves 4.84fJ/C-s·mm², the smallest ever reported. The fabricated circuits consume 0.05mm² and 3.05μW/channel, exhibiting 63.8dB SNDR, 3.02 NEF, and 4.56NEF²V_DD.

Original language	English
Title of host publication	2015 Symposium on VLSI Circuits, VLSI Circuits 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	C112-C113
ISBN (Electronic)	9784863485020
DOIs	https://doi.org/10.1109/VLSIC.2015.7231344
Publication status	Published - 2015 Aug 31
Event	29th Annual Symposium on VLSI Circuits, VLSI Circuits 2015 - Kyoto, Japan Duration: 2015 Jun 17 → 2015 Jun 19

Publication series

Name	IEEE Symposium on VLSI Circuits, Digest of Technical Papers
Volume	2015-August

Conference

Conference	29th Annual Symposium on VLSI Circuits, VLSI Circuits 2015
Country/Territory	Japan
City	Kyoto
Period	15/6/17 → 15/6/19

Bibliographical note

Publisher Copyright:
© 2015 JSAP.

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Access to Document

10.1109/VLSIC.2015.7231344

Cite this

Park, S. Y., Cho, J., Na, K., & Yoon, E. (2015). Toward 1024-channel parallel neural recording: Modular Δ-ΔΣ Analog front-end architecture with 4.84fJ/C-s·mm² energy-area product. In 2015 Symposium on VLSI Circuits, VLSI Circuits 2015 (pp. C112-C113). [7231344] (IEEE Symposium on VLSI Circuits, Digest of Technical Papers; Vol. 2015-August). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSIC.2015.7231344

Park, Sung Yun ; Cho, Jihyun ; Na, Kyounghwan et al. / Toward 1024-channel parallel neural recording : Modular Δ-ΔΣ Analog front-end architecture with 4.84fJ/C-s·mm² energy-area product. 2015 Symposium on VLSI Circuits, VLSI Circuits 2015. Institute of Electrical and Electronics Engineers Inc., 2015. pp. C112-C113 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

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abstract = "We report an energy- and area-efficient modular analog front-end (AFE) architecture incorporating Δ-modulated ΔΣ (Δ-ΔΣ) signal acquisition for 1,024-channel brain activity monitoring platforms. The AFE employs spectrum-equalizing and continuous-time (CT)-ΔΣ quantization to make use of the inherent spectral characteristics of brain signals. The dynamic range (DR) of the neural signals has been compressed by 27dB (spectrum equalization). The energy-area product is the most critical figure of merit for massively-parallel recordings and the AFE achieves 4.84fJ/C-s·mm2, the smallest ever reported. The fabricated circuits consume 0.05mm2 and 3.05μW/channel, exhibiting 63.8dB SNDR, 3.02 NEF, and 4.56NEF2VDD.",

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Park, SY, Cho, J, Na, K & Yoon, E 2015, Toward 1024-channel parallel neural recording: Modular Δ-ΔΣ Analog front-end architecture with 4.84fJ/C-s·mm² energy-area product. in 2015 Symposium on VLSI Circuits, VLSI Circuits 2015., 7231344, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, vol. 2015-August, Institute of Electrical and Electronics Engineers Inc., pp. C112-C113, 29th Annual Symposium on VLSI Circuits, VLSI Circuits 2015, Kyoto, Japan, 15/6/17. https://doi.org/10.1109/VLSIC.2015.7231344

Toward 1024-channel parallel neural recording : Modular Δ-ΔΣ Analog front-end architecture with 4.84fJ/C-s·mm² energy-area product. / Park, Sung Yun; Cho, Jihyun; Na, Kyounghwan et al.

2015 Symposium on VLSI Circuits, VLSI Circuits 2015. Institute of Electrical and Electronics Engineers Inc., 2015. p. C112-C113 7231344 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers; Vol. 2015-August).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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Park SY, Cho J, Na K, Yoon E. Toward 1024-channel parallel neural recording: Modular Δ-ΔΣ Analog front-end architecture with 4.84fJ/C-s·mm² energy-area product. In 2015 Symposium on VLSI Circuits, VLSI Circuits 2015. Institute of Electrical and Electronics Engineers Inc. 2015. p. C112-C113. 7231344. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). doi: 10.1109/VLSIC.2015.7231344