This paper focuses on the engineering trade-offs in designing capacitor voltage balancing schemes for modular multilevel converters (MMC) HVDC: regulation performance and switching loss. MMC is driven by the on/off switch operation of numerous submodules and the key design concern is balancing submodule capacitor voltages minimizing switching transition among submodules because it represents the voltage regulation performance and system loss. This paper first introduces the state-ofthe-art MMC-HVDC submodule capacitor voltage balancing methods reported in the literatures and discusses the trade-offs in designing these methods for HVDC application. This paper further proposes a submodule capacitor balancing scheme exploiting a control signal to flexibly interchange between the on-state and the off-state submodules. The proposed scheme enables desired performance-based voltage regulation and avoids unnecessary switching transitions among submodules, consequently reducing the switching loss. The flexibility and controllability particularly fit in high-level MMC HVDC applications where the aforementioned design trade-offs become more crucial. Simulation studies for MMC HVDC are performed to demonstrate the validity and effectiveness of the proposed capacitor voltage balancing algorithm.
Bibliographical noteFunding Information:
This work was supported by the National Research Foundation of Korea(NRF) grant funded by the Korea government (MSIP) (No.2010-0028509) and also supported by the Yonsei University Research Fund of 2015.
© The Korean Institute of Electrical Engineers.
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering