Dynamic logic is much susceptible to noise, specially in ultra deep submicron technology. The keeper transistor has to be carefully sized to maintain noise margin without much speed penalty. In this paper, we analyze the keeper transistor sizing with respect to the size of NMOS transistors in the evaluation tree. Based on the analytical results, we propose a keeper transistor sizing method. HSPICE simulation results show that the proposed keeper transistor sizing method can be broadly applied to all domino logic gates.
|Number of pages||6|
|Journal||Proceedings of the IEEE Great Lakes Symposium on VLSI|
|Publication status||Published - 2001 Jan 1|
|Event||11th Great Lakes Sysmposium on VLSI (GLSVLSI 2001) - West Lafayette, IN, United States|
Duration: 2001 Mar 22 → 2001 Mar 23
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering