Transistor sizing for reliable domino logic design in dual threshold voltage technologies

S. O. Jung, K. W. Kim, S. M. Kang

Research output: Contribution to journalConference article

2 Citations (Scopus)

Abstract

Dynamic logic is much susceptible to noise, specially in ultra deep submicron technology. The keeper transistor has to be carefully sized to maintain noise margin without much speed penalty. In this paper, we analyze the keeper transistor sizing with respect to the size of NMOS transistors in the evaluation tree. Based on the analytical results, we propose a keeper transistor sizing method. HSPICE simulation results show that the proposed keeper transistor sizing method can be broadly applied to all domino logic gates.

Original languageEnglish
Pages (from-to)133-138
Number of pages6
JournalProceedings of the IEEE Great Lakes Symposium on VLSI
Publication statusPublished - 2001 Jan 1
Event11th Great Lakes Sysmposium on VLSI (GLSVLSI 2001) - West Lafayette, IN, United States
Duration: 2001 Mar 222001 Mar 23

Fingerprint

Logic design
Threshold voltage
Transistors
Logic gates

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

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Transistor sizing for reliable domino logic design in dual threshold voltage technologies. / Jung, S. O.; Kim, K. W.; Kang, S. M.

In: Proceedings of the IEEE Great Lakes Symposium on VLSI, 01.01.2001, p. 133-138.

Research output: Contribution to journalConference article

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