Transition-delay test methodology for designs with self-gating

Jihye Kim, Sangjun Lee, Minho Moon, Sungho Kang

Research output: Chapter in Book/Report/Conference proceedingConference contribution


Power reduction is one of the most important design factors for system-on-chip. The self-gating method is used for power reduction in clock networks, which is one of the main factors of dynamic power consumption. However, scan test patterns can be increased by the self-gating insertion. It is observed that the test pattern increase is very severe for transition delay (TD) faults with the experimental results that over 250% of TD test patterns are increased with XOR selfgating insertion in the industrial circuits. In this paper, a new efficient TD test methodology is proposed which uses the data selectable self-gating (DSSG) structure. The experimental results show that using the new methodology, the average TD pattern increase ratio has dropped to under 50%.

Original languageEnglish
Title of host publicationProceedings - 2019 International SoC Design Conference, ISOCC 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages2
ISBN (Electronic)9781728124780
Publication statusPublished - 2019 Oct 1
Event16th International System-on-Chip Design Conference, ISOCC 2019 - Jeju, Korea, Republic of
Duration: 2019 Oct 62019 Oct 9

Publication series

NameProceedings - 2019 International SoC Design Conference, ISOCC 2019


Conference16th International System-on-Chip Design Conference, ISOCC 2019
Country/TerritoryKorea, Republic of

Bibliographical note

Funding Information:
This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIT) (No. 2019R1A2C3011079).

Publisher Copyright:
© 2019 IEEE.

All Science Journal Classification (ASJC) codes

  • Signal Processing
  • Electrical and Electronic Engineering
  • Instrumentation
  • Artificial Intelligence
  • Hardware and Architecture


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