Transition-delay test methodology for designs with self-gating

Jihye Kim; Sangjun Lee; Minho Moon; Sungho Kang

doi:10.1109/ISOCC47750.2019.9078524

Transition-delay test methodology for designs with self-gating

Jihye Kim, Sangjun Lee, Minho Moon, Sungho Kang

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Power reduction is one of the most important design factors for system-on-chip. The self-gating method is used for power reduction in clock networks, which is one of the main factors of dynamic power consumption. However, scan test patterns can be increased by the self-gating insertion. It is observed that the test pattern increase is very severe for transition delay (TD) faults with the experimental results that over 250% of TD test patterns are increased with XOR selfgating insertion in the industrial circuits. In this paper, a new efficient TD test methodology is proposed which uses the data selectable self-gating (DSSG) structure. The experimental results show that using the new methodology, the average TD pattern increase ratio has dropped to under 50%.

Original language	English
Title of host publication	Proceedings - 2019 International SoC Design Conference, ISOCC 2019
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	93-94
Number of pages	2
ISBN (Electronic)	9781728124780
DOIs	https://doi.org/10.1109/ISOCC47750.2019.9078524
Publication status	Published - 2019 Oct 1
Event	16th International System-on-Chip Design Conference, ISOCC 2019 - Jeju, Korea, Republic of Duration: 2019 Oct 6 → 2019 Oct 9

Publication series

Name	Proceedings - 2019 International SoC Design Conference, ISOCC 2019
Volume	2019-January

Conference

Conference	16th International System-on-Chip Design Conference, ISOCC 2019
Country/Territory	Korea, Republic of
City	Jeju
Period	19/10/6 → 19/10/9

Bibliographical note

Funding Information:
This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIT) (No. 2019R1A2C3011079).

Publisher Copyright:
© 2019 IEEE.

All Science Journal Classification (ASJC) codes

Signal Processing
Electrical and Electronic Engineering
Instrumentation
Artificial Intelligence
Hardware and Architecture

Access to Document

10.1109/ISOCC47750.2019.9078524

Cite this

Kim, J., Lee, S., Moon, M., & Kang, S. (2019). Transition-delay test methodology for designs with self-gating. In Proceedings - 2019 International SoC Design Conference, ISOCC 2019 (pp. 93-94). [9078524] (Proceedings - 2019 International SoC Design Conference, ISOCC 2019; Vol. 2019-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISOCC47750.2019.9078524

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abstract = "Power reduction is one of the most important design factors for system-on-chip. The self-gating method is used for power reduction in clock networks, which is one of the main factors of dynamic power consumption. However, scan test patterns can be increased by the self-gating insertion. It is observed that the test pattern increase is very severe for transition delay (TD) faults with the experimental results that over 250% of TD test patterns are increased with XOR selfgating insertion in the industrial circuits. In this paper, a new efficient TD test methodology is proposed which uses the data selectable self-gating (DSSG) structure. The experimental results show that using the new methodology, the average TD pattern increase ratio has dropped to under 50%.",

author = "Jihye Kim and Sangjun Lee and Minho Moon and Sungho Kang",

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Kim, J, Lee, S, Moon, M & Kang, S 2019, Transition-delay test methodology for designs with self-gating. in Proceedings - 2019 International SoC Design Conference, ISOCC 2019., 9078524, Proceedings - 2019 International SoC Design Conference, ISOCC 2019, vol. 2019-January, Institute of Electrical and Electronics Engineers Inc., pp. 93-94, 16th International System-on-Chip Design Conference, ISOCC 2019, Jeju, Korea, Republic of, 19/10/6. https://doi.org/10.1109/ISOCC47750.2019.9078524

Transition-delay test methodology for designs with self-gating. / Kim, Jihye; Lee, Sangjun; Moon, Minho et al.

Proceedings - 2019 International SoC Design Conference, ISOCC 2019. Institute of Electrical and Electronics Engineers Inc., 2019. p. 93-94 9078524 (Proceedings - 2019 International SoC Design Conference, ISOCC 2019; Vol. 2019-January).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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Transition-delay test methodology for designs with self-gating

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