The poor quality of the die stacking process for 3-D integrated circuits can result in the failure of the process in the through-silicon-vias (TSVs) in dense regions. Previous works use the same number of redundant TSVs and architectures that do not consider the TSV density. A repair architecture and an appropriate number of redundant TSVs, which are chosen considering the TSV density, are required for an improved repair rate. This paper proposes a method that demonstrates such an architecture and calculates the required number of TSVs. The method has a high repair rate for clustered faults, and wire-length problems are solved using the shift-based repair method.
|Number of pages||5|
|Journal||IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems|
|Publication status||Published - 2019 Jan|
Bibliographical noteFunding Information:
Manuscript received September 2, 2016; revised March 29, 2017; accepted February 10, 2018. Date of publication February 21, 2018; date of current version December 19, 2018. This research was supported by the MOTIE(Ministry of Trade, Industry & Energy) (10052875) and KSRC(Korea Semiconductor Research Consortium) support program for the development of the future semiconductor device. This paper was recommended by Associate Editor S. Patil. (Corresponding author: Sungho Kang.) The authors are with the Department of Electrical and Electronic Engineering, Yonsei University, Seoul 03722, South Korea (e-mail: email@example.com; firstname.lastname@example.org; email@example.com).
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All Science Journal Classification (ASJC) codes
- Computer Graphics and Computer-Aided Design
- Electrical and Electronic Engineering