Ultra-thin gate dielectric reliability projections

M. Moosa; A. Haggag; N. Liu; S. Kalpat; M. Kuffler; D. Menke; P. Abramowitz; M. E. Ramón; H. H. Tseng; T. Y. Luo; S. Lim; P. Grudowski; J. Jiang; B. W. Min; C. Weintraub; J. Chen; S. Wong; C. Paquette; G. Anderson; P. J. Tobin; B. E. White; M. Mendicino

doi:10.1109/icicdt.2005.1502609

Ultra-thin gate dielectric reliability projections

M. Moosa, A. Haggag, N. Liu, S. Kalpat, M. Kuffler, D. Menke, P. Abramowitz, M. E. Ramón, H. H. Tseng, T. Y. Luo, S. Lim, P. Grudowski, J. Jiang, B. W. Min, C. Weintraub, J. Chen, S. Wong, C. Paquette, G. Anderson, P. J. TobinB. E. White, M. Mendicino

Department of Chemical and Biomolecular Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

Phenomenological time-dependent dielectric breakdown (TDDB) and bias-temperature instability (BTI) models are demonstrated to enable reasonably accurate reliability projections for several generations of silicon oxynitride-based transistors and circuits with EOT down to ∼1.3nm. Furthermore, while reliability and performance can be traded-off by engineering the gate dielectric coupled with device integration, benchmarking of published data suggests that the reliability achievable at each transistor node falls within an intrinsically plausible range for similar dielectric films. A preliminary investigation of high-k dielectric device reliability suggests that a similar methodology can be adopted to project the reliability of scaled high-k films.

Original language	English
Title of host publication	2005 International Conference on Integrated Circuit Design and Technology, ICICDT
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	129-133
Number of pages	5
ISBN (Print)	0780390814, 9780780390812
DOIs	https://doi.org/10.1109/icicdt.2005.1502609
Publication status	Published - 2005
Event	2005 International Conference on Integrated Circuit Design and Technology, ICICDT - Austin, TX, United States Duration: 2005 May 9 → 2005 May 11

Publication series

Name	2005 International Conference on Integrated Circuit Design and Technology, ICICDT

Other

Other	2005 International Conference on Integrated Circuit Design and Technology, ICICDT
Country/Territory	United States
City	Austin, TX
Period	05/5/9 → 05/5/11

All Science Journal Classification (ASJC) codes

Engineering(all)

Access to Document

10.1109/icicdt.2005.1502609

Cite this

Moosa, M., Haggag, A., Liu, N., Kalpat, S., Kuffler, M., Menke, D., Abramowitz, P., Ramón, M. E., Tseng, H. H., Luo, T. Y., Lim, S., Grudowski, P., Jiang, J., Min, B. W., Weintraub, C., Chen, J., Wong, S., Paquette, C., Anderson, G., ... Mendicino, M. (2005). Ultra-thin gate dielectric reliability projections. In 2005 International Conference on Integrated Circuit Design and Technology, ICICDT (pp. 129-133). [F3] (2005 International Conference on Integrated Circuit Design and Technology, ICICDT). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/icicdt.2005.1502609

Moosa, M. ; Haggag, A. ; Liu, N. ; Kalpat, S. ; Kuffler, M. ; Menke, D. ; Abramowitz, P. ; Ramón, M. E. ; Tseng, H. H. ; Luo, T. Y. ; Lim, S. ; Grudowski, P. ; Jiang, J. ; Min, B. W. ; Weintraub, C. ; Chen, J. ; Wong, S. ; Paquette, C. ; Anderson, G. ; Tobin, P. J. ; White, B. E. ; Mendicino, M. / Ultra-thin gate dielectric reliability projections. 2005 International Conference on Integrated Circuit Design and Technology, ICICDT. Institute of Electrical and Electronics Engineers Inc., 2005. pp. 129-133 (2005 International Conference on Integrated Circuit Design and Technology, ICICDT).

@inproceedings{d90e4560828a43989ef86583f1bb2ac6,

title = "Ultra-thin gate dielectric reliability projections",

abstract = "Phenomenological time-dependent dielectric breakdown (TDDB) and bias-temperature instability (BTI) models are demonstrated to enable reasonably accurate reliability projections for several generations of silicon oxynitride-based transistors and circuits with EOT down to ∼1.3nm. Furthermore, while reliability and performance can be traded-off by engineering the gate dielectric coupled with device integration, benchmarking of published data suggests that the reliability achievable at each transistor node falls within an intrinsically plausible range for similar dielectric films. A preliminary investigation of high-k dielectric device reliability suggests that a similar methodology can be adopted to project the reliability of scaled high-k films.",

author = "M. Moosa and A. Haggag and N. Liu and S. Kalpat and M. Kuffler and D. Menke and P. Abramowitz and Ram{\'o}n, {M. E.} and Tseng, {H. H.} and Luo, {T. Y.} and S. Lim and P. Grudowski and J. Jiang and Min, {B. W.} and C. Weintraub and J. Chen and S. Wong and C. Paquette and G. Anderson and Tobin, {P. J.} and White, {B. E.} and M. Mendicino",

year = "2005",

doi = "10.1109/icicdt.2005.1502609",

language = "English",

isbn = "0780390814",

series = "2005 International Conference on Integrated Circuit Design and Technology, ICICDT",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "129--133",

booktitle = "2005 International Conference on Integrated Circuit Design and Technology, ICICDT",

address = "United States",

note = "2005 International Conference on Integrated Circuit Design and Technology, ICICDT ; Conference date: 09-05-2005 Through 11-05-2005",

}

Moosa, M, Haggag, A, Liu, N, Kalpat, S, Kuffler, M, Menke, D, Abramowitz, P, Ramón, ME, Tseng, HH, Luo, TY, Lim, S, Grudowski, P, Jiang, J, Min, BW, Weintraub, C, Chen, J, Wong, S, Paquette, C, Anderson, G, Tobin, PJ, White, BE & Mendicino, M 2005, Ultra-thin gate dielectric reliability projections. in 2005 International Conference on Integrated Circuit Design and Technology, ICICDT., F3, 2005 International Conference on Integrated Circuit Design and Technology, ICICDT, Institute of Electrical and Electronics Engineers Inc., pp. 129-133, 2005 International Conference on Integrated Circuit Design and Technology, ICICDT, Austin, TX, United States, 05/5/9. https://doi.org/10.1109/icicdt.2005.1502609

Ultra-thin gate dielectric reliability projections. / Moosa, M.; Haggag, A.; Liu, N.; Kalpat, S.; Kuffler, M.; Menke, D.; Abramowitz, P.; Ramón, M. E.; Tseng, H. H.; Luo, T. Y.; Lim, S.; Grudowski, P.; Jiang, J.; Min, B. W.; Weintraub, C.; Chen, J.; Wong, S.; Paquette, C.; Anderson, G.; Tobin, P. J.; White, B. E.; Mendicino, M.

2005 International Conference on Integrated Circuit Design and Technology, ICICDT. Institute of Electrical and Electronics Engineers Inc., 2005. p. 129-133 F3 (2005 International Conference on Integrated Circuit Design and Technology, ICICDT).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Ultra-thin gate dielectric reliability projections

AU - Moosa, M.

AU - Haggag, A.

AU - Liu, N.

AU - Kalpat, S.

AU - Kuffler, M.

AU - Menke, D.

AU - Abramowitz, P.

AU - Ramón, M. E.

AU - Tseng, H. H.

AU - Luo, T. Y.

AU - Lim, S.

AU - Grudowski, P.

AU - Jiang, J.

AU - Min, B. W.

AU - Weintraub, C.

AU - Chen, J.

AU - Wong, S.

AU - Paquette, C.

AU - Anderson, G.

AU - Tobin, P. J.

AU - White, B. E.

AU - Mendicino, M.

PY - 2005

Y1 - 2005

N2 - Phenomenological time-dependent dielectric breakdown (TDDB) and bias-temperature instability (BTI) models are demonstrated to enable reasonably accurate reliability projections for several generations of silicon oxynitride-based transistors and circuits with EOT down to ∼1.3nm. Furthermore, while reliability and performance can be traded-off by engineering the gate dielectric coupled with device integration, benchmarking of published data suggests that the reliability achievable at each transistor node falls within an intrinsically plausible range for similar dielectric films. A preliminary investigation of high-k dielectric device reliability suggests that a similar methodology can be adopted to project the reliability of scaled high-k films.

AB - Phenomenological time-dependent dielectric breakdown (TDDB) and bias-temperature instability (BTI) models are demonstrated to enable reasonably accurate reliability projections for several generations of silicon oxynitride-based transistors and circuits with EOT down to ∼1.3nm. Furthermore, while reliability and performance can be traded-off by engineering the gate dielectric coupled with device integration, benchmarking of published data suggests that the reliability achievable at each transistor node falls within an intrinsically plausible range for similar dielectric films. A preliminary investigation of high-k dielectric device reliability suggests that a similar methodology can be adopted to project the reliability of scaled high-k films.

UR - http://www.scopus.com/inward/record.url?scp=25844495378&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=25844495378&partnerID=8YFLogxK

U2 - 10.1109/icicdt.2005.1502609

DO - 10.1109/icicdt.2005.1502609

M3 - Conference contribution

AN - SCOPUS:25844495378

SN - 0780390814

SN - 9780780390812

T3 - 2005 International Conference on Integrated Circuit Design and Technology, ICICDT

SP - 129

EP - 133

BT - 2005 International Conference on Integrated Circuit Design and Technology, ICICDT

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2005 International Conference on Integrated Circuit Design and Technology, ICICDT

Y2 - 9 May 2005 through 11 May 2005

ER -

Moosa M, Haggag A, Liu N, Kalpat S, Kuffler M, Menke D et al. Ultra-thin gate dielectric reliability projections. In 2005 International Conference on Integrated Circuit Design and Technology, ICICDT. Institute of Electrical and Electronics Engineers Inc. 2005. p. 129-133. F3. (2005 International Conference on Integrated Circuit Design and Technology, ICICDT). https://doi.org/10.1109/icicdt.2005.1502609

Ultra-thin gate dielectric reliability projections

Abstract

Publication series

Other

All Science Journal Classification (ASJC) codes

Access to Document

Other files and links

Fingerprint

Cite this