V th variation and strain control of high Ge% thin SiGe channels by millisecond anneal realizing high performance pMOSFET beyond 16nm node

S. H. Lee, J. Huang, P. Majhi, P. D. Kirsch, B. G. Min, C. S. Park, J. Oh, W. Y. Loh, C. Y. Kang, B. Sassman, P. Y. Hung, S. McCoy, J. Chen, B. Wu, G. Moori, D. Heh, C. Young, G. Bersuker, H. H. Tseng, S. K. BanerjeeR. Jammy

Research output: Chapter in Book/Report/Conference proceedingConference contribution

18 Citations (Scopus)

Abstract

We have studied key parameters for controlling threshold voltage (V th) variation and strain maintenance of gate first SiGe channel pMOSFETs. By overcoming 1) Ge diffusion and 2) strain relaxation during source/drain activation, we for the first time demonstrate high Ge% (50%) SiGe channel with millisecond flash anneal. Optimizing the thermal budget with millisecond anneal keeps the V th variation same to Si unlike RTA anneal while still having 2.8x mobility gain. We achieved high performance SiGe pMOSFETs with appropriate V th [-0.2∼-0.3V], ∼1nm EOT and superior NBTI [<30mV] reliability for the integration of SiGe channel for pMOSFETs.

Original languageEnglish
Title of host publication2009 Symposium on VLSI Technology, VLSIT 2009
Pages74-75
Number of pages2
Publication statusPublished - 2009 Nov 16
Event2009 Symposium on VLSI Technology, VLSIT 2009 - Kyoto, Japan
Duration: 2009 Jun 162009 Jun 18

Publication series

NameDigest of Technical Papers - Symposium on VLSI Technology
ISSN (Print)0743-1562

Other

Other2009 Symposium on VLSI Technology, VLSIT 2009
CountryJapan
CityKyoto
Period09/6/1609/6/18

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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    Lee, S. H., Huang, J., Majhi, P., Kirsch, P. D., Min, B. G., Park, C. S., Oh, J., Loh, W. Y., Kang, C. Y., Sassman, B., Hung, P. Y., McCoy, S., Chen, J., Wu, B., Moori, G., Heh, D., Young, C., Bersuker, G., Tseng, H. H., ... Jammy, R. (2009). V th variation and strain control of high Ge% thin SiGe channels by millisecond anneal realizing high performance pMOSFET beyond 16nm node. In 2009 Symposium on VLSI Technology, VLSIT 2009 (pp. 74-75). [5200639] (Digest of Technical Papers - Symposium on VLSI Technology).