This letter presents a high power V-W band CMOS distributed step attenuator with a low phase imbalance. Thirteen nMOS varistors are periodically placed in a t-line and change the attenuation in a step up to 10 dB. For high power handling, four-stacked and biased nMOS transistors are used for the varistor. Shunt t-lines under the varistors compensate for the phase imbalance of the attenuation states. The total chip size is 0.38 mm2 excluding pads. The insertion loss of the attenuator is 5.6-11.2 dB at 50-110 GHz. The return loss is <- 15 dB at 50-110 GHz with the rms phase imbalance of <1.4° and the input 1 dB compression point of 17 dBm.
All Science Journal Classification (ASJC) codes
- Condensed Matter Physics
- Electrical and Electronic Engineering