V-W band CMOS distributed step attenuator with low phase imbalance

Kyungwon Kim, Hyo Sung Lee, Byung Wook Min

Research output: Contribution to journalArticle

10 Citations (Scopus)

Abstract

This letter presents a high power V-W band CMOS distributed step attenuator with a low phase imbalance. Thirteen nMOS varistors are periodically placed in a t-line and change the attenuation in a step up to 10 dB. For high power handling, four-stacked and biased nMOS transistors are used for the varistor. Shunt t-lines under the varistors compensate for the phase imbalance of the attenuation states. The total chip size is 0.38 mm2 excluding pads. The insertion loss of the attenuator is 5.6-11.2 dB at 50-110 GHz. The return loss is <- 15 dB at 50-110 GHz with the rms phase imbalance of <1.4° and the input 1 dB compression point of 17 dBm.

Original languageEnglish
Article number6832611
Pages (from-to)548-550
Number of pages3
JournalIEEE Microwave and Wireless Components Letters
Volume24
Issue number8
DOIs
Publication statusPublished - 2014 Aug

All Science Journal Classification (ASJC) codes

  • Condensed Matter Physics
  • Electrical and Electronic Engineering

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