Abstract
A figure of merit (FOM) for a CMOS system on chip (SoC) is proposed to correctly assess different CMOS SoCs in the near-threshold voltage (Vth) region, where the supply voltage (VDD) is slightly higher than Vth. When VDD is scaled down to near Vth, the drain current becomes greatly sensitive to VDD or Vth; furthermore, the energy exhibits the same sensitivity as that in the super-Vth region. The conventional FOM, the energy-delay product (EDP), is not applicable in the near-Vth region, because the EDP does not consider the sensitivity difference between the energy and the delay. The procedure for establishing an FOM that can appropriately consider the sensitivity difference by fitting the characteristics of a transistor is first introduced. Then, the FOM developed by the proposed procedure is applied to the examples of an inverter chain operating in both the super-Vth and near-Vth regions, which verifies that the proposed FOM is appropriate in the near-Vth region, whereas the EDP is not.
| Original language | English |
|---|---|
| Article number | A32 |
| Pages (from-to) | 1754-1759 |
| Number of pages | 6 |
| Journal | IEEE Transactions on Electron Devices |
| Volume | 62 |
| Issue number | 6 |
| DOIs | |
| Publication status | Published - 2015 Jun 1 |
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All Science Journal Classification (ASJC) codes
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering
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Variation-aware figure of merit for integrated circuit in near-threshold region. / Jeong, Hanwool; Yang, Younghwi; Song, Seung Chul; Wang, Joseph; Yeap, Geoffrey; Jung, Seong Ook.
In: IEEE Transactions on Electron Devices, Vol. 62, No. 6, A32, 01.06.2015, p. 1754-1759.Research output: Contribution to journal › Article
TY - JOUR
T1 - Variation-aware figure of merit for integrated circuit in near-threshold region
AU - Jeong, Hanwool
AU - Yang, Younghwi
AU - Song, Seung Chul
AU - Wang, Joseph
AU - Yeap, Geoffrey
AU - Jung, Seong Ook
PY - 2015/6/1
Y1 - 2015/6/1
N2 - A figure of merit (FOM) for a CMOS system on chip (SoC) is proposed to correctly assess different CMOS SoCs in the near-threshold voltage (Vth) region, where the supply voltage (VDD) is slightly higher than Vth. When VDD is scaled down to near Vth, the drain current becomes greatly sensitive to VDD or Vth; furthermore, the energy exhibits the same sensitivity as that in the super-Vth region. The conventional FOM, the energy-delay product (EDP), is not applicable in the near-Vth region, because the EDP does not consider the sensitivity difference between the energy and the delay. The procedure for establishing an FOM that can appropriately consider the sensitivity difference by fitting the characteristics of a transistor is first introduced. Then, the FOM developed by the proposed procedure is applied to the examples of an inverter chain operating in both the super-Vth and near-Vth regions, which verifies that the proposed FOM is appropriate in the near-Vth region, whereas the EDP is not.
AB - A figure of merit (FOM) for a CMOS system on chip (SoC) is proposed to correctly assess different CMOS SoCs in the near-threshold voltage (Vth) region, where the supply voltage (VDD) is slightly higher than Vth. When VDD is scaled down to near Vth, the drain current becomes greatly sensitive to VDD or Vth; furthermore, the energy exhibits the same sensitivity as that in the super-Vth region. The conventional FOM, the energy-delay product (EDP), is not applicable in the near-Vth region, because the EDP does not consider the sensitivity difference between the energy and the delay. The procedure for establishing an FOM that can appropriately consider the sensitivity difference by fitting the characteristics of a transistor is first introduced. Then, the FOM developed by the proposed procedure is applied to the examples of an inverter chain operating in both the super-Vth and near-Vth regions, which verifies that the proposed FOM is appropriate in the near-Vth region, whereas the EDP is not.
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UR - http://www.scopus.com/inward/citedby.url?scp=85028209548&partnerID=8YFLogxK
U2 - 10.1109/TED.2015.2424220
DO - 10.1109/TED.2015.2424220
M3 - Article
AN - SCOPUS:85028209548
VL - 62
SP - 1754
EP - 1759
JO - IEEE Transactions on Electron Devices
JF - IEEE Transactions on Electron Devices
SN - 0018-9383
IS - 6
M1 - A32
ER -