Variation-aware figure of merit for integrated circuit in near-threshold region

Hanwool Jeong, Younghwi Yang, Seung Chul Song, Joseph Wang, Geoffrey Yeap, Seong Ook Jung

Research output: Contribution to journalArticlepeer-review

4 Citations (Scopus)

Abstract

A figure of merit (FOM) for a CMOS system on chip (SoC) is proposed to correctly assess different CMOS SoCs in the near-threshold voltage (Vth) region, where the supply voltage (VDD) is slightly higher than Vth. When VDD is scaled down to near Vth, the drain current becomes greatly sensitive to VDD or Vth; furthermore, the energy exhibits the same sensitivity as that in the super-Vth region. The conventional FOM, the energy-delay product (EDP), is not applicable in the near-Vth region, because the EDP does not consider the sensitivity difference between the energy and the delay. The procedure for establishing an FOM that can appropriately consider the sensitivity difference by fitting the characteristics of a transistor is first introduced. Then, the FOM developed by the proposed procedure is applied to the examples of an inverter chain operating in both the super-Vth and near-Vth regions, which verifies that the proposed FOM is appropriate in the near-Vth region, whereas the EDP is not.

Original languageEnglish
Article numberA32
Pages (from-to)1754-1759
Number of pages6
JournalIEEE Transactions on Electron Devices
Volume62
Issue number6
DOIs
Publication statusPublished - 2015 Jun 1

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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