A figure of merit (FOM) for a CMOS system on chip (SoC) is proposed to correctly assess different CMOS SoCs in the near-threshold voltage (Vth) region, where the supply voltage (VDD) is slightly higher than Vth. When VDD is scaled down to near Vth, the drain current becomes greatly sensitive to VDD or Vth; furthermore, the energy exhibits the same sensitivity as that in the super-Vth region. The conventional FOM, the energy-delay product (EDP), is not applicable in the near-Vth region, because the EDP does not consider the sensitivity difference between the energy and the delay. The procedure for establishing an FOM that can appropriately consider the sensitivity difference by fitting the characteristics of a transistor is first introduced. Then, the FOM developed by the proposed procedure is applied to the examples of an inverter chain operating in both the super-Vth and near-Vth regions, which verifies that the proposed FOM is appropriate in the near-Vth region, whereas the EDP is not.
All Science Journal Classification (ASJC) codes
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering