Variation-Tolerant and low power look-up table (LUT) using spin-Torque transfer magnetic RAM for non-volatile field programmable gate array (FPGA)

Kangwook Jo, Kyungseon Cho, Hongil Yoon

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

The non-volatile field programmable gate array (FPGA) is a promising candidate for the ultra-low-power computing due to its flexibility. However, the non-volatile devices have a critical drawback of reliability due to the process variations in read operation. We propose a novel look-up table scheme using the spin-Torque transfer magnetic RAM with high variation tolerance and low power consumption. The proposed 8- input look-up table (LUT) has a 74.4% smaller read power consumption than that of the conventional 8-input SRAM-based LUT. The area of the proposed LUT is comparable to that of the conventional SRAM-based LUT.

Original languageEnglish
Title of host publicationISOCC 2016 - International SoC Design Conference
Subtitle of host publicationSmart SoC for Intelligent Things
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages101-102
Number of pages2
ISBN (Electronic)9781467393089
DOIs
Publication statusPublished - 2016 Dec 27
Event13th International SoC Design Conference, ISOCC 2016 - Jeju, Korea, Republic of
Duration: 2016 Oct 232016 Oct 26

Publication series

NameISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things

Other

Other13th International SoC Design Conference, ISOCC 2016
Country/TerritoryKorea, Republic of
CityJeju
Period16/10/2316/10/26

Bibliographical note

Publisher Copyright:
© 2016 IEEE.

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Instrumentation

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