Abstract
The non-volatile field programmable gate array (FPGA) is a promising candidate for the ultra-low-power computing due to its flexibility. However, the non-volatile devices have a critical drawback of reliability due to the process variations in read operation. We propose a novel look-up table scheme using the spin-Torque transfer magnetic RAM with high variation tolerance and low power consumption. The proposed 8- input look-up table (LUT) has a 74.4% smaller read power consumption than that of the conventional 8-input SRAM-based LUT. The area of the proposed LUT is comparable to that of the conventional SRAM-based LUT.
| Original language | English |
|---|---|
| Title of host publication | ISOCC 2016 - International SoC Design Conference |
| Subtitle of host publication | Smart SoC for Intelligent Things |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 101-102 |
| Number of pages | 2 |
| ISBN (Electronic) | 9781467393089 |
| DOIs | |
| Publication status | Published - 2016 Dec 27 |
| Event | 13th International SoC Design Conference, ISOCC 2016 - Jeju, Korea, Republic of Duration: 2016 Oct 23 → 2016 Oct 26 |
Other
| Other | 13th International SoC Design Conference, ISOCC 2016 |
|---|---|
| Country | Korea, Republic of |
| City | Jeju |
| Period | 16/10/23 → 16/10/26 |
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All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Electrical and Electronic Engineering
- Instrumentation
Cite this
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Variation-Tolerant and low power look-up table (LUT) using spin-Torque transfer magnetic RAM for non-volatile field programmable gate array (FPGA). / Jo, Kangwook; Cho, Kyungseon; Yoon, Hongil.
ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things. Institute of Electrical and Electronics Engineers Inc., 2016. p. 101-102 7799753.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
TY - GEN
T1 - Variation-Tolerant and low power look-up table (LUT) using spin-Torque transfer magnetic RAM for non-volatile field programmable gate array (FPGA)
AU - Jo, Kangwook
AU - Cho, Kyungseon
AU - Yoon, Hongil
PY - 2016/12/27
Y1 - 2016/12/27
N2 - The non-volatile field programmable gate array (FPGA) is a promising candidate for the ultra-low-power computing due to its flexibility. However, the non-volatile devices have a critical drawback of reliability due to the process variations in read operation. We propose a novel look-up table scheme using the spin-Torque transfer magnetic RAM with high variation tolerance and low power consumption. The proposed 8- input look-up table (LUT) has a 74.4% smaller read power consumption than that of the conventional 8-input SRAM-based LUT. The area of the proposed LUT is comparable to that of the conventional SRAM-based LUT.
AB - The non-volatile field programmable gate array (FPGA) is a promising candidate for the ultra-low-power computing due to its flexibility. However, the non-volatile devices have a critical drawback of reliability due to the process variations in read operation. We propose a novel look-up table scheme using the spin-Torque transfer magnetic RAM with high variation tolerance and low power consumption. The proposed 8- input look-up table (LUT) has a 74.4% smaller read power consumption than that of the conventional 8-input SRAM-based LUT. The area of the proposed LUT is comparable to that of the conventional SRAM-based LUT.
UR - http://www.scopus.com/inward/record.url?scp=85010399990&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85010399990&partnerID=8YFLogxK
U2 - 10.1109/ISOCC.2016.7799753
DO - 10.1109/ISOCC.2016.7799753
M3 - Conference contribution
AN - SCOPUS:85010399990
SP - 101
EP - 102
BT - ISOCC 2016 - International SoC Design Conference
PB - Institute of Electrical and Electronics Engineers Inc.
ER -