Variation-tolerant wl driving scheme for high-capacity NAND flash memory

Junyoung Ko; Younghwi Yang; Jisu Kim; Cheonan Lee; Young Sun Min; Jinyoung Chun; Moo Sung Kim; Seong Ook Jung

doi:10.1109/TVLSI.2019.2912081

Variation-tolerant wl driving scheme for high-capacity NAND flash memory

Junyoung Ko, Younghwi Yang, Jisu Kim, Cheonan Lee, Young Sun Min, Jinyoung Chun, Moo Sung Kim, Seong Ook Jung

Department of Electrical and Electronic Engineering

Research output: Contribution to journal › Article › peer-review

4 Citations (Scopus)

Abstract

Research on a word-line (WL) driving scheme is essential because the effect of WL parasitic resistance and capacitance (RC) is more severe for high-capacity NAND flash memories. The WL under-driving scheme (WLUDS) mitigates the effect of parasitic RC by reducing the coupling capacitance between WLs. However, WLUDS increases the cell threshold voltage ( V-{\mathrm {th}} ) distribution because of parasitic RC variation, which causes an overshoot of the programming voltage ( V-{\mathrm {PGM}} ). In this study, we propose the variation-tolerant WL under-driving scheme (VTWLUDS) to reduce the effect of parasitic RC variation and V-{\mathrm {PGM}} overshoot through the use of a three-phase V-{\mathrm {PGM}} control. We also introduce the fast-verify WL driving scheme (FVWLDS) to reduce the effect of parasitic RC variation in the verify operation. We verified VTWLUDS and FVWLDS by performing an HSPICE simulation with Samsung's transistor model for a NAND peripheral circuit. The simulation results showed that VTWLUDS achieved a sufficient V-{\mathrm {th}} shift during the programming operation regardless of the WL parasitic RC variation. By using VTWLUDS and FVWLDS, we achieved 1304 \mu \text{s} of total programming time ( T-{\mathrm {PROG}} ) for a 512-Gb planar-type NAND flash memory.

Original language	English
Article number	8704315
Pages (from-to)	1828-1839
Number of pages	12
Journal	IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume	27
Issue number	8
DOIs	https://doi.org/10.1109/TVLSI.2019.2912081
Publication status	Published - 2019 Aug

Bibliographical note

Funding Information:
Manuscript received November 29, 2018; revised March 10, 2019; accepted April 7, 2019. Date of publication May 1, 2019; date of current version July 24, 2019. This work was supported by the FLASH Design Team, Memory Division, Samsung Electronics Co., Ltd., South Korea. (Corresponding author: Seong-Ook Jung.) J. Ko, Y. Yang, and S.-O. Jung are with the School of Electrical and Electronic Engineering, Yonsei University, Seoul 120-749, South Korea (e-mail: sjung@yonsei.ac.kr).

Publisher Copyright:
© 1993-2012 IEEE.

All Science Journal Classification (ASJC) codes

Software
Hardware and Architecture
Electrical and Electronic Engineering

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10.1109/TVLSI.2019.2912081

Cite this

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title = "Variation-tolerant wl driving scheme for high-capacity NAND flash memory",

abstract = "Research on a word-line (WL) driving scheme is essential because the effect of WL parasitic resistance and capacitance (RC) is more severe for high-capacity NAND flash memories. The WL under-driving scheme (WLUDS) mitigates the effect of parasitic RC by reducing the coupling capacitance between WLs. However, WLUDS increases the cell threshold voltage ( V-{\mathrm {th}} ) distribution because of parasitic RC variation, which causes an overshoot of the programming voltage ( V-{\mathrm {PGM}} ). In this study, we propose the variation-tolerant WL under-driving scheme (VTWLUDS) to reduce the effect of parasitic RC variation and V-{\mathrm {PGM}} overshoot through the use of a three-phase V-{\mathrm {PGM}} control. We also introduce the fast-verify WL driving scheme (FVWLDS) to reduce the effect of parasitic RC variation in the verify operation. We verified VTWLUDS and FVWLDS by performing an HSPICE simulation with Samsung's transistor model for a NAND peripheral circuit. The simulation results showed that VTWLUDS achieved a sufficient V-{\mathrm {th}} shift during the programming operation regardless of the WL parasitic RC variation. By using VTWLUDS and FVWLDS, we achieved 1304 \mu \text{s} of total programming time ( T-{\mathrm {PROG}} ) for a 512-Gb planar-type NAND flash memory.",

author = "Junyoung Ko and Younghwi Yang and Jisu Kim and Cheonan Lee and Min, {Young Sun} and Jinyoung Chun and Kim, {Moo Sung} and Jung, {Seong Ook}",

note = "Funding Information: Manuscript received November 29, 2018; revised March 10, 2019; accepted April 7, 2019. Date of publication May 1, 2019; date of current version July 24, 2019. This work was supported by the FLASH Design Team, Memory Division, Samsung Electronics Co., Ltd., South Korea. (Corresponding author: Seong-Ook Jung.) J. Ko, Y. Yang, and S.-O. Jung are with the School of Electrical and Electronic Engineering, Yonsei University, Seoul 120-749, South Korea (e-mail: sjung@yonsei.ac.kr). Publisher Copyright: {\textcopyright} 1993-2012 IEEE.",

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AU - Yang, Younghwi

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AU - Lee, Cheonan

AU - Min, Young Sun

AU - Chun, Jinyoung

AU - Kim, Moo Sung

AU - Jung, Seong Ook

N1 - Funding Information: Manuscript received November 29, 2018; revised March 10, 2019; accepted April 7, 2019. Date of publication May 1, 2019; date of current version July 24, 2019. This work was supported by the FLASH Design Team, Memory Division, Samsung Electronics Co., Ltd., South Korea. (Corresponding author: Seong-Ook Jung.) J. Ko, Y. Yang, and S.-O. Jung are with the School of Electrical and Electronic Engineering, Yonsei University, Seoul 120-749, South Korea (e-mail: sjung@yonsei.ac.kr). Publisher Copyright: © 1993-2012 IEEE.

PY - 2019/8

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N2 - Research on a word-line (WL) driving scheme is essential because the effect of WL parasitic resistance and capacitance (RC) is more severe for high-capacity NAND flash memories. The WL under-driving scheme (WLUDS) mitigates the effect of parasitic RC by reducing the coupling capacitance between WLs. However, WLUDS increases the cell threshold voltage ( V-{\mathrm {th}} ) distribution because of parasitic RC variation, which causes an overshoot of the programming voltage ( V-{\mathrm {PGM}} ). In this study, we propose the variation-tolerant WL under-driving scheme (VTWLUDS) to reduce the effect of parasitic RC variation and V-{\mathrm {PGM}} overshoot through the use of a three-phase V-{\mathrm {PGM}} control. We also introduce the fast-verify WL driving scheme (FVWLDS) to reduce the effect of parasitic RC variation in the verify operation. We verified VTWLUDS and FVWLDS by performing an HSPICE simulation with Samsung's transistor model for a NAND peripheral circuit. The simulation results showed that VTWLUDS achieved a sufficient V-{\mathrm {th}} shift during the programming operation regardless of the WL parasitic RC variation. By using VTWLUDS and FVWLDS, we achieved 1304 \mu \text{s} of total programming time ( T-{\mathrm {PROG}} ) for a 512-Gb planar-type NAND flash memory.

AB - Research on a word-line (WL) driving scheme is essential because the effect of WL parasitic resistance and capacitance (RC) is more severe for high-capacity NAND flash memories. The WL under-driving scheme (WLUDS) mitigates the effect of parasitic RC by reducing the coupling capacitance between WLs. However, WLUDS increases the cell threshold voltage ( V-{\mathrm {th}} ) distribution because of parasitic RC variation, which causes an overshoot of the programming voltage ( V-{\mathrm {PGM}} ). In this study, we propose the variation-tolerant WL under-driving scheme (VTWLUDS) to reduce the effect of parasitic RC variation and V-{\mathrm {PGM}} overshoot through the use of a three-phase V-{\mathrm {PGM}} control. We also introduce the fast-verify WL driving scheme (FVWLDS) to reduce the effect of parasitic RC variation in the verify operation. We verified VTWLUDS and FVWLDS by performing an HSPICE simulation with Samsung's transistor model for a NAND peripheral circuit. The simulation results showed that VTWLUDS achieved a sufficient V-{\mathrm {th}} shift during the programming operation regardless of the WL parasitic RC variation. By using VTWLUDS and FVWLDS, we achieved 1304 \mu \text{s} of total programming time ( T-{\mathrm {PROG}} ) for a 512-Gb planar-type NAND flash memory.

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Variation-tolerant wl driving scheme for high-capacity NAND flash memory

Abstract

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