Variation-tolerant wl driving scheme for high-capacity NAND flash memory

Junyoung Ko, Younghwi Yang, Jisu Kim, Cheonan Lee, Young Sun Min, Jinyoung Chun, Moo Sung Kim, Seong Ook Jung

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

Research on a word-line (WL) driving scheme is essential because the effect of WL parasitic resistance and capacitance (RC) is more severe for high-capacity NAND flash memories. The WL under-driving scheme (WLUDS) mitigates the effect of parasitic RC by reducing the coupling capacitance between WLs. However, WLUDS increases the cell threshold voltage ( V-{\mathrm {th}} ) distribution because of parasitic RC variation, which causes an overshoot of the programming voltage ( V-{\mathrm {PGM}} ). In this study, we propose the variation-tolerant WL under-driving scheme (VTWLUDS) to reduce the effect of parasitic RC variation and V-{\mathrm {PGM}} overshoot through the use of a three-phase V-{\mathrm {PGM}} control. We also introduce the fast-verify WL driving scheme (FVWLDS) to reduce the effect of parasitic RC variation in the verify operation. We verified VTWLUDS and FVWLDS by performing an HSPICE simulation with Samsung's transistor model for a NAND peripheral circuit. The simulation results showed that VTWLUDS achieved a sufficient V-{\mathrm {th}} shift during the programming operation regardless of the WL parasitic RC variation. By using VTWLUDS and FVWLDS, we achieved 1304 \mu \text{s} of total programming time ( T-{\mathrm {PROG}} ) for a 512-Gb planar-type NAND flash memory.

Original languageEnglish
Article number8704315
Pages (from-to)1828-1839
Number of pages12
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume27
Issue number8
DOIs
Publication statusPublished - 2019 Aug

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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