Vertically and laterally self-aligned double-layer of nanocrystals in nanopatterned dielectric layer for nanocrystal floating gate memory device

Quanli Hu, Tae Kwang Eom, Soo Hyun Kim, Hyung Jun Kim, Hyun Ho Lee, Yong Sang Kim, Du Yeol Ryu, Ki Bum Kim, Tae Sik Yoon

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The formation of vertically and laterally self-aligned double-layer of CdSe colloidal nanocrystals (NCs) in nanopatterned dielectric layer on Si substrate was demonstrated by repeating dip-coating process for NC deposition and atomic layer deposition (ALD) of Al 2O 3 layer. A nanopatterned-SiO 2/Si substrate was formed by patterning with self-assembled diblock copolymer. After the selective deposition of the 1 st NC layer inside SiO 2 nanopattern by dip-coating, an Al 2O 3 interdielectric layer and the 2 nd NC layer in Al 2O 3 nanopattern were sequentially deposited. The capacitance-voltage measurement of Al-gate/ALD-Al 2O 3(25nm)/2 nd-CdSe-NCs/ALD-Al 2O 3(2nm)/1 st-CdSe-NCs/nanopatterned-Si0 2(15nm)/p- Si substrate structure showed the flatband voltage shift resulting from the charging of NCs.

Original languageEnglish
Title of host publicationLow-Dimensional Nanoscale Electronic and Photonic Devices 4
Pages75-82
Number of pages8
Volume33
Edition9
DOIs
Publication statusPublished - 2010 Dec 1
EventLow-Dimensional Nanoscale Electronic and Photonic Devices 4 - 218th ECS Meeting - Las Vegas, NV, United States
Duration: 2010 Oct 102010 Oct 15

Other

OtherLow-Dimensional Nanoscale Electronic and Photonic Devices 4 - 218th ECS Meeting
CountryUnited States
CityLas Vegas, NV
Period10/10/1010/10/15

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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  • Cite this

    Hu, Q., Eom, T. K., Kim, S. H., Kim, H. J., Lee, H. H., Kim, Y. S., Ryu, D. Y., Kim, K. B., & Yoon, T. S. (2010). Vertically and laterally self-aligned double-layer of nanocrystals in nanopatterned dielectric layer for nanocrystal floating gate memory device. In Low-Dimensional Nanoscale Electronic and Photonic Devices 4 (9 ed., Vol. 33, pp. 75-82) https://doi.org/10.1149/1.3493685