Abstract
In this paper, we propose a video encoder/decoder architecture for HD-DVCRs based on the `Specifications of Consumer-Use Digital VCRs'. To reduce hardware complexity a novel QNO selection algorithm is developed. The arranging algorithm of a segment is implemented with minimal memory and most hardware is shared in the encoding/decoding process. The proposed architecture's target operating frequency is 54 MHz and it will be fabricated using 3-layer metal 0.6 um CMOS process technology.
Original language | English |
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Pages (from-to) | 54-55 |
Number of pages | 2 |
Journal | Digest of Technical Papers - IEEE International Conference on Consumer Electronics |
Publication status | Published - 1997 |
Event | Proceedings of the 1997 16th International Conference on Consumer Electronics, ICCE - Rosemont, IL, USA Duration: 1997 Jun 11 → 1997 Jun 13 |
All Science Journal Classification (ASJC) codes
- Industrial and Manufacturing Engineering
- Electrical and Electronic Engineering