Video encoder/decoder architecture for consumer-use HD-DVCRs

Sang Jun An, Heung Chul Oh, Tae Young Lee, Yong Hwan Lee, Jae Seok Kim, Yong Surk Lee

Research output: Contribution to journalConference article

Abstract

In this paper, we propose a video encoder/decoder architecture for HD-DVCRs based on the `Specifications of Consumer-Use Digital VCRs'. To reduce hardware complexity a novel QNO selection algorithm is developed. The arranging algorithm of a segment is implemented with minimal memory and most hardware is shared in the encoding/decoding process. The proposed architecture's target operating frequency is 54 MHz and it will be fabricated using 3-layer metal 0.6 um CMOS process technology.

Original languageEnglish
Pages (from-to)54-55
Number of pages2
JournalDigest of Technical Papers - IEEE International Conference on Consumer Electronics
Publication statusPublished - 1997 Dec 1

Fingerprint

Videocassette recorders
Computer hardware
Decoding
Specifications
Hardware
Data storage equipment
Metals

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Industrial and Manufacturing Engineering

Cite this

An, Sang Jun ; Oh, Heung Chul ; Lee, Tae Young ; Lee, Yong Hwan ; Kim, Jae Seok ; Lee, Yong Surk. / Video encoder/decoder architecture for consumer-use HD-DVCRs. In: Digest of Technical Papers - IEEE International Conference on Consumer Electronics. 1997 ; pp. 54-55.
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Video encoder/decoder architecture for consumer-use HD-DVCRs. / An, Sang Jun; Oh, Heung Chul; Lee, Tae Young; Lee, Yong Hwan; Kim, Jae Seok; Lee, Yong Surk.

In: Digest of Technical Papers - IEEE International Conference on Consumer Electronics, 01.12.1997, p. 54-55.

Research output: Contribution to journalConference article

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AU - Oh, Heung Chul

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AU - Lee, Yong Surk

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