Abstract
Modern GPUs require tens of thousands of concurrent threads to fully utilize the massive amount of processing resources. However, thread concurrency in GPUs can be diminished either due to shortage of thread scheduling structures (scheduling limit), such as available program counters and single instruction multiple thread stacks, or due to shortage of on-chip memory (capacity limit), such as register file and shared memory. Our evaluations show that in practice concurrency in many general purpose applications running on GPUs is curtailed by the scheduling limit rather than the capacity limit. Maximizing the utilization of on-chip memory resources without unduly increasing the scheduling complexity is a key goal of this paper. This paper proposes a Virtual Thread (VT) architecture which assigns Cooperative Thread Arrays (CTAs) up to the capacity limit, while ignoring the scheduling limit. However, to reduce the logic complexity of managing more threads concurrently, we propose to place CTAs into active and inactive states, such that the number of active CTAs still respects the scheduling limit. When all the warps in an active CTA hit a long latency stall, the active CTA is context switched out and the next ready CTA takes its place. We exploit the fact that both active and inactive CTAs still fit within the capacity limit which obviates the need to save and restore large amounts of CTA state. Thus VT significantly reduces performance penalties of CTA swapping. By swapping between active and inactive states, VT can exploit higher degree of thread level parallelism without increasing logic complexity. Our simulation results show that VT improves performance by 23.9% on average.
| Original language | English |
|---|---|
| Title of host publication | Proceedings - 2016 43rd International Symposium on Computer Architecture, ISCA 2016 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 609-621 |
| Number of pages | 13 |
| ISBN (Electronic) | 9781467389471 |
| DOIs | |
| Publication status | Published - 2016 Aug 24 |
| Event | 43rd International Symposium on Computer Architecture, ISCA 2016 - Seoul, Korea, Republic of Duration: 2016 Jun 18 → 2016 Jun 22 |
Publication series
| Name | Proceedings - 2016 43rd International Symposium on Computer Architecture, ISCA 2016 |
|---|
Other
| Other | 43rd International Symposium on Computer Architecture, ISCA 2016 |
|---|---|
| Country | Korea, Republic of |
| City | Seoul |
| Period | 16/6/18 → 16/6/22 |
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All Science Journal Classification (ASJC) codes
- Hardware and Architecture
Cite this
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Virtual Thread : Maximizing Thread-Level Parallelism beyond GPU Scheduling Limit. / Yoon, Myung Kuk; Kim, Keunsoo; Lee, Sangpil; Ro, Won Woo; Annavaram, Murali.
Proceedings - 2016 43rd International Symposium on Computer Architecture, ISCA 2016. Institute of Electrical and Electronics Engineers Inc., 2016. p. 609-621 7551426 (Proceedings - 2016 43rd International Symposium on Computer Architecture, ISCA 2016).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
TY - GEN
T1 - Virtual Thread
T2 - Maximizing Thread-Level Parallelism beyond GPU Scheduling Limit
AU - Yoon, Myung Kuk
AU - Kim, Keunsoo
AU - Lee, Sangpil
AU - Ro, Won Woo
AU - Annavaram, Murali
PY - 2016/8/24
Y1 - 2016/8/24
N2 - Modern GPUs require tens of thousands of concurrent threads to fully utilize the massive amount of processing resources. However, thread concurrency in GPUs can be diminished either due to shortage of thread scheduling structures (scheduling limit), such as available program counters and single instruction multiple thread stacks, or due to shortage of on-chip memory (capacity limit), such as register file and shared memory. Our evaluations show that in practice concurrency in many general purpose applications running on GPUs is curtailed by the scheduling limit rather than the capacity limit. Maximizing the utilization of on-chip memory resources without unduly increasing the scheduling complexity is a key goal of this paper. This paper proposes a Virtual Thread (VT) architecture which assigns Cooperative Thread Arrays (CTAs) up to the capacity limit, while ignoring the scheduling limit. However, to reduce the logic complexity of managing more threads concurrently, we propose to place CTAs into active and inactive states, such that the number of active CTAs still respects the scheduling limit. When all the warps in an active CTA hit a long latency stall, the active CTA is context switched out and the next ready CTA takes its place. We exploit the fact that both active and inactive CTAs still fit within the capacity limit which obviates the need to save and restore large amounts of CTA state. Thus VT significantly reduces performance penalties of CTA swapping. By swapping between active and inactive states, VT can exploit higher degree of thread level parallelism without increasing logic complexity. Our simulation results show that VT improves performance by 23.9% on average.
AB - Modern GPUs require tens of thousands of concurrent threads to fully utilize the massive amount of processing resources. However, thread concurrency in GPUs can be diminished either due to shortage of thread scheduling structures (scheduling limit), such as available program counters and single instruction multiple thread stacks, or due to shortage of on-chip memory (capacity limit), such as register file and shared memory. Our evaluations show that in practice concurrency in many general purpose applications running on GPUs is curtailed by the scheduling limit rather than the capacity limit. Maximizing the utilization of on-chip memory resources without unduly increasing the scheduling complexity is a key goal of this paper. This paper proposes a Virtual Thread (VT) architecture which assigns Cooperative Thread Arrays (CTAs) up to the capacity limit, while ignoring the scheduling limit. However, to reduce the logic complexity of managing more threads concurrently, we propose to place CTAs into active and inactive states, such that the number of active CTAs still respects the scheduling limit. When all the warps in an active CTA hit a long latency stall, the active CTA is context switched out and the next ready CTA takes its place. We exploit the fact that both active and inactive CTAs still fit within the capacity limit which obviates the need to save and restore large amounts of CTA state. Thus VT significantly reduces performance penalties of CTA swapping. By swapping between active and inactive states, VT can exploit higher degree of thread level parallelism without increasing logic complexity. Our simulation results show that VT improves performance by 23.9% on average.
UR - http://www.scopus.com/inward/record.url?scp=84988336029&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84988336029&partnerID=8YFLogxK
U2 - 10.1109/ISCA.2016.59
DO - 10.1109/ISCA.2016.59
M3 - Conference contribution
AN - SCOPUS:84988336029
T3 - Proceedings - 2016 43rd International Symposium on Computer Architecture, ISCA 2016
SP - 609
EP - 621
BT - Proceedings - 2016 43rd International Symposium on Computer Architecture, ISCA 2016
PB - Institute of Electrical and Electronics Engineers Inc.
ER -