Clock network plays the most significant role in power consumption in IC design. Since a clock network normally has a high switching ratio, power optimization of the clock network is one of the best solutions to minimize dynamic power and total power in modern IC designs. The clock network is synthesized based on an initial flip-flop placement. The number of clock buffers and their sizes are decided by the initial placement. Moreover, clock wires, which are the major sources of clock power consumption, are also constructed based on the flip-flop placement. As a result, the flip-flop placement determines the quality of the clock network. In this article, we propose a new clock network optimization method to reduce the dynamic power consumption of clock network. The method first creates virtual tiles over the entire design area and selects the most effective columns to align flip-flops in lines. Once the effective columns are determined, flip-flops are relocated based on the virtual tiles in the columns considering the minimum moving distance. By aligning flip-flops, it is possible to significantly reduce both wire capacitance and wire length. Since it does not change the clock structure, unlike the conventional clock network optimization techniques which use multibit flip-flop or register bank, there is no degradation in timing or other constraints. Experimental results show that the proposed method reduces the wire capacitance, wire length, and via count up to 23.2%, 10.2%, and 16.4%, respectively, in five industrial intellectual property (IP) designs. The reduction in clock network power is 14.1% on average.
|Number of pages||13|
|Journal||IEEE Transactions on Very Large Scale Integration (VLSI) Systems|
|Publication status||Published - 2020 May 1|
Bibliographical noteFunding Information:
Dr. Imran was a recipient of scholarship by the Higher Education Commission of Pakistan for M.S. and Ph.D. studies.
Manuscript received June 27, 2019; revised October 16, 2019 and December 7, 2019; accepted December 29, 2019. Date of publication February 21, 2020; date of current version April 24, 2020. This work was supported in part by the Basic Science Research Program through the National Research Foundation of Korea by the Ministry of Education under Grant NRF-2018R1D1A1B07049842 and Grant 2015R1D1A1A01058856, in part by the Ministry of Trade, Industry Energy (MOTIE) under Grant 10080594, and in part by the Korea Semiconductor Research Consortium (KSRC) Support Program for the Development of the Future Semiconductor Device. (Corresponding author: Joon-Sung Yang.) Taehyun Kwon is with the Department of Semiconductor and Display Engineering, Sungkyunkwan University, Seoul, South Korea, and also with the System LSI Division, Samsung Electronics, Seoul, South Korea.
© 1993-2012 IEEE.
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Electrical and Electronic Engineering