Three-dimensional (3-D) integration offers a promising solution to the technology scaling barriers. Reliability of the 3-D Integrated Circuits (ICs) is highly dependent on the integrity of the underlying interconnect. Through Silicon Via (TSV) based 3-D ICs would suffer from low yield due to the faults in TSVs. In addition, TSVs introduce stress and noise in the substrate. Adding redundant TSVs for repairing the faulty ones has commonly been proposed to improve the yield of TSV-based 3-D ICs. The existing TSV repair approaches employ a number of spare TSVs in a group of signal TSVs. We propose a TSV virtualization based repair architecture which utilizes a single redundant TSV to repair multiple faulty TSVs. The proposed architecture relies on transmitting multiple bits through a single TSV using multi-level voltage quantization. It makes efficient use of the TSV redundancies in repairing the faulty TSVs. With less number of spare TSVs, the proposed architecture can reduce the area overhead by more than 70%. Reduction in the TSV count allows greater interconnect density and helps to mitigate the TSV-induced noise and stresses. Alternatively, for a similar number of spare TSVs, the proposed method can enhance the fault tolerance capability of the conventional approaches thus leading to an enhanced chip yield. The eye diagram simulations using an electrical model of the TSV show a reduction of less than 5% in noise margin when using a 16-level voltage quantization at a data rate of 5 Gbps which is typical for 3-D integration applications.
|Number of pages||12|
|Publication status||Published - 2020|
Bibliographical noteFunding Information:
This work was supported in part by the Institute of Information and Communications Technology Planning and Evaluation (IITP) Grant funded by the Korean Government (MSIT), through the AI Graduate School Support Program, under Grant 2019-0-00421, in part by the Basic Science Research Program through the National Research Foundation of Korea by the Ministry of Education under Grant NRF-2018R1D1A1B07049842, in part by the Ministry of Trade, Industry Energy (MOTIE) under Grant 10080594, in part by the Korea Semiconductor Research Consortium (KSRC) Support Program for the Development of the Future Semiconductor Device, in part by the Competency Development Program for Industry Specialists of the Korean Ministry of Trade, Industry and Energy (MOTIE), Operated by the Korea Institute for Advancement of Technology (KIAT) under Grant N0001883, and in part by the HRD Program for Intelligent semiconductor Industry.
© 2013 IEEE.
All Science Journal Classification (ASJC) codes
- Computer Science(all)
- Materials Science(all)