VLSI architecture design of rake receivers for cdma2000 systems

Seongjoo Lee; Jaseok Kim

doi:10.1109/SIPS.2002.1049706

VLSI architecture design of rake receivers for cdma2000 systems

Seongjoo Lee, Jaseok Kim

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

We propose low-complexity architecture for rake receivers in cdma2000 systems. The hardware cost of rake receivers is significantly increased in cdma2000 systems, because rake receivers should demodulate multi-path signals transmitted through multiple sub-carriers. We, therefore, present a novel architecture which adopts a multifinger structure, arithmetic units shared by multi-fingers, and time-deskew buffers using a pre-combining technique. The results show that the proposed receiver reduces the hardware complexity by about 49.4% compared with a conventional one.

Original language	English
Title of host publication	IEEE Workshop on Signal Processing Systems, SIPS 2002
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	183-188
Number of pages	6
ISBN (Electronic)	0780375874
DOIs	https://doi.org/10.1109/SIPS.2002.1049706
Publication status	Published - 2002
Event	16th IEEE Workshop on Signal Processing Systems, SIPS 2002 - San Diego, United States Duration: 2002 Oct 16 → 2002 Oct 18

Publication series

Name	IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation
Volume	2002-January
ISSN (Print)	1520-6130

Conference

Conference	16th IEEE Workshop on Signal Processing Systems, SIPS 2002
Country/Territory	United States
City	San Diego
Period	02/10/16 → 02/10/18

Bibliographical note

Publisher Copyright:
© 2002 IEEE.

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering
Signal Processing
Applied Mathematics
Hardware and Architecture

Access to Document

10.1109/SIPS.2002.1049706

Cite this

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title = "VLSI architecture design of rake receivers for cdma2000 systems",

abstract = "We propose low-complexity architecture for rake receivers in cdma2000 systems. The hardware cost of rake receivers is significantly increased in cdma2000 systems, because rake receivers should demodulate multi-path signals transmitted through multiple sub-carriers. We, therefore, present a novel architecture which adopts a multifinger structure, arithmetic units shared by multi-fingers, and time-deskew buffers using a pre-combining technique. The results show that the proposed receiver reduces the hardware complexity by about 49.4% compared with a conventional one.",

author = "Seongjoo Lee and Jaseok Kim",

note = "Publisher Copyright: {\textcopyright} 2002 IEEE.; 16th IEEE Workshop on Signal Processing Systems, SIPS 2002 ; Conference date: 16-10-2002 Through 18-10-2002",

year = "2002",

doi = "10.1109/SIPS.2002.1049706",

language = "English",

series = "IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation",

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Lee, S & Kim, J 2002, VLSI architecture design of rake receivers for cdma2000 systems. in IEEE Workshop on Signal Processing Systems, SIPS 2002., 1049706, IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation, vol. 2002-January, Institute of Electrical and Electronics Engineers Inc., pp. 183-188, 16th IEEE Workshop on Signal Processing Systems, SIPS 2002, San Diego, United States, 02/10/16. https://doi.org/10.1109/SIPS.2002.1049706

VLSI architecture design of rake receivers for cdma2000 systems. / Lee, Seongjoo; Kim, Jaseok.

IEEE Workshop on Signal Processing Systems, SIPS 2002. Institute of Electrical and Electronics Engineers Inc., 2002. p. 183-188 1049706 (IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation; Vol. 2002-January).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AU - Kim, Jaseok

PY - 2002

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N2 - We propose low-complexity architecture for rake receivers in cdma2000 systems. The hardware cost of rake receivers is significantly increased in cdma2000 systems, because rake receivers should demodulate multi-path signals transmitted through multiple sub-carriers. We, therefore, present a novel architecture which adopts a multifinger structure, arithmetic units shared by multi-fingers, and time-deskew buffers using a pre-combining technique. The results show that the proposed receiver reduces the hardware complexity by about 49.4% compared with a conventional one.

AB - We propose low-complexity architecture for rake receivers in cdma2000 systems. The hardware cost of rake receivers is significantly increased in cdma2000 systems, because rake receivers should demodulate multi-path signals transmitted through multiple sub-carriers. We, therefore, present a novel architecture which adopts a multifinger structure, arithmetic units shared by multi-fingers, and time-deskew buffers using a pre-combining technique. The results show that the proposed receiver reduces the hardware complexity by about 49.4% compared with a conventional one.

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VLSI architecture design of rake receivers for cdma2000 systems

Abstract

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Conference

Bibliographical note

All Science Journal Classification (ASJC) codes

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