VLSI architecture of CDMA rake receiver with low hardware complexity for PCS

Seongjoo Lee, Sangyun Hwang, Jaeseok Kim

Research output: Contribution to journalConference article

3 Citations (Scopus)


In this paper, we propose a VLSI architecture of CDMA rake receiver which consists of a searcher and three fingers having some shared hardware blocks to reduce the hardware complexity. The proposed rake receiver suitable for IS-95 based CDMA PCS system was designed using VHDL and it contains about 30 K logic gates. We also implemented our system on FPGA chips and it was successfully tested.

Original languageEnglish
Pages (from-to)160-161
Number of pages2
JournalDigest of Technical Papers - IEEE International Conference on Consumer Electronics
Publication statusPublished - 1998 Jan 1
EventProceedings of the 1998 17th Conference on Consumer Electronics - Los Angeles, CA, USA
Duration: 1998 Jun 21998 Jun 4


All Science Journal Classification (ASJC) codes

  • Industrial and Manufacturing Engineering
  • Electrical and Electronic Engineering

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