VLSI DESIGN OF HIGH-SPEED, LOW-AREA ADDITION CIRCUITRY.

Tackdon Han, David A. Carlson, Steven P. Levitan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Citations (Scopus)

Abstract

The authors study area-time tradeoffs in VLSI for prefix computation using a graph representation of this problem. Since the problem is intimately related to binary addition, the results imply the existence of area-time efficient VLSI adders. They extend previous work on algorithms for prefix computation to the general case of bounded fan-in, fan-out m (m greater than equivalent to 2), and reduce the depth of the algorithm from 2log//mn-1 to log//mn plus 1. Using the algorithm, the authors design VLSI adders having area O(nlog n) whose delay time is the lowest possible value, i. e. , the fastest possible area-efficient VLSI adders.

Original languageEnglish
Title of host publicationUnknown Host Publication Title
PublisherIEEE
Pages418-422
Number of pages5
ISBN (Print)0818608021
Publication statusPublished - 1987 Dec 1

    Fingerprint

All Science Journal Classification (ASJC) codes

  • Engineering(all)

Cite this

Han, T., Carlson, D. A., & Levitan, S. P. (1987). VLSI DESIGN OF HIGH-SPEED, LOW-AREA ADDITION CIRCUITRY. In Unknown Host Publication Title (pp. 418-422). IEEE.