VLSI DESIGN OF HIGH-SPEED, LOW-AREA ADDITION CIRCUITRY.

The authors study area-time tradeoffs in VLSI for prefix computation using a graph representation of this problem. Since the problem is intimately related to binary addition, the results imply the existence of area-time efficient VLSI adders. They extend previous work on algorithms for prefix computation to the general case of bounded fan-in, fan-out m (m greater than equivalent to 2), and reduce the depth of the algorithm from 2log//mn-1 to log//mn plus 1. Using the algorithm, the authors design VLSI adders having area O(nlog n) whose delay time is the lowest possible value, i. e. , the fastest possible area-efficient VLSI adders.