A CMOS 4-bit phase shifter is designed for W-band applications using a 65-nm CMOS process. Switched-delay-type 90°, 45° , and 22.5° 1-bit phase shifters are designed to have high power-handling capability using a signal line bias voltage. The power and phase compression of 90° , 45°, and 22.5° phase shifters are analyzed, and the phase shifters are optimally cascaded for high power and phase compression points. The measured insertion loss of the 4-bit phase shifter is-25\pm 2.1 dB , and the root mean square (RMS) gain error of the 16 different phase states is 1.1 dB at 77 GHz. An input and output return loss is less than-8 dB at 70-85 GHz. The phase shifter has the RMS phase error of 7.2° at 77 GHz and is less than 11.25° at 75-85 GHz. The measured minimum 1-dB power compression point of 16 different phase states is 15.0 dBm. The high input power also compresses the phase adjustment range and increases the phase error, which is limited to 11.25° up to the input power of 21 dBm. The phase shifter consumes no dc current and occupies a small chip area of 0.122 mm2, excluding pads.
|Number of pages||5|
|Journal||IEEE Transactions on Circuits and Systems II: Express Briefs|
|Publication status||Published - 2015 Jan 1|
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering