Main memory systems based on phase-change random access memory (PRAM) have been actively researched due to low static power consumption, which is adequate to mobile consumer electronics. However, PRAMs require wear-leveling, which incur performance overhead, to compensate their limited life-time. Even though many works have discussed the overhead in terms of write latency, read latency is also affected and the degradation is even severer since PRAM read is faster than write. Consequently, this paper proposes a wear-leveling scheduler that reduces the effect of wear-leveling overhead on read latency. The proposed method which can cooperate with various wear-leveling algorithms enables wear-leveling only when no read request is issued for a period longer than the pre-defined threshold. In spite of simplicity, a PRAM-based memory system equipped with the proposed method achieves 50% shorter read latency without affecting wear-leveling performance.