WIR: Warp Instruction Reuse to Minimize Repeated Computations in GPUs

Keunsoo Kim, Won Woo Ro

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

Warp instructions with an identical arithmetic operation on same input values produce the identical computation results. This paper proposes warp instruction reuse to allow such repeated warp instructions to reuse previous computation results instead of actually executing the instructions. Bypassing register reading, functional unit, and register writing operations improves energy efficiency. This reuse technique is especially beneficial for GPUs since a GPU warp register is usually as wide as thousands of bits. In addition, we propose warp register reuse which allows identical warp register values to share a single physical register through register renaming. The register reuse technique enables to see if different logical warp registers have an identical value by only looking at their physical warp register IDs. Based on this observation, warp register reuse helps to perform all necessary operations for warp instruction reuse with register IDs, which is substantially more efficient than directly manipulating register values. Performance evaluation shows that 20.5% SM energy and 10.7% GPU energy can be saved by allowing 18.7% of warp instructions to reuse prior results.

Original languageEnglish
Title of host publicationProceedings - 24th IEEE International Symposium on High Performance Computer Architecture, HPCA 2018
PublisherIEEE Computer Society
Pages389-402
Number of pages14
ISBN (Electronic)9781538636596
DOIs
Publication statusPublished - 2018 Mar 27
Event24th IEEE International Symposium on High Performance Computer Architecture, HPCA 2018 - Vienna, Austria
Duration: 2018 Feb 242018 Feb 28

Publication series

NameProceedings - International Symposium on High-Performance Computer Architecture
Volume2018-February
ISSN (Print)1530-0897

Other

Other24th IEEE International Symposium on High Performance Computer Architecture, HPCA 2018
CountryAustria
CityVienna
Period18/2/2418/2/28

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All Science Journal Classification (ASJC) codes

  • Hardware and Architecture

Cite this

Kim, K., & Ro, W. W. (2018). WIR: Warp Instruction Reuse to Minimize Repeated Computations in GPUs. In Proceedings - 24th IEEE International Symposium on High Performance Computer Architecture, HPCA 2018 (pp. 389-402). (Proceedings - International Symposium on High-Performance Computer Architecture; Vol. 2018-February). IEEE Computer Society. https://doi.org/10.1109/HPCA.2018.00041