Warp instructions with an identical arithmetic operation on same input values produce the identical computation results. This paper proposes warp instruction reuse to allow such repeated warp instructions to reuse previous computation results instead of actually executing the instructions. Bypassing register reading, functional unit, and register writing operations improves energy efficiency. This reuse technique is especially beneficial for GPUs since a GPU warp register is usually as wide as thousands of bits. In addition, we propose warp register reuse which allows identical warp register values to share a single physical register through register renaming. The register reuse technique enables to see if different logical warp registers have an identical value by only looking at their physical warp register IDs. Based on this observation, warp register reuse helps to perform all necessary operations for warp instruction reuse with register IDs, which is substantially more efficient than directly manipulating register values. Performance evaluation shows that 20.5% SM energy and 10.7% GPU energy can be saved by allowing 18.7% of warp instructions to reuse prior results.
|Title of host publication||Proceedings - 24th IEEE International Symposium on High Performance Computer Architecture, HPCA 2018|
|Publisher||IEEE Computer Society|
|Number of pages||14|
|Publication status||Published - 2018 Mar 27|
|Event||24th IEEE International Symposium on High Performance Computer Architecture, HPCA 2018 - Vienna, Austria|
Duration: 2018 Feb 24 → 2018 Feb 28
|Name||Proceedings - International Symposium on High-Performance Computer Architecture|
|Other||24th IEEE International Symposium on High Performance Computer Architecture, HPCA 2018|
|Period||18/2/24 → 18/2/28|
Bibliographical noteFunding Information:
This work is supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIP) (No. NRF-2015R1A2A2A01008281) and by the ICT R&D program of MSIP/IITP. [No. 2016-0-00140, Development of Application Program Optimization Tools for High Performance Computing Systems]
© 2018 IEEE.
All Science Journal Classification (ASJC) codes
- Hardware and Architecture