WL under-driving scheme with decremental step voltage and incremental step time for high-capacity NAND flash memory

Junyoung Ko, Younghwi Yang, Seongook Jung, Jisu Kim, Cheon An Lee, Young Sun Min, Jinyoung Chun, Moosung Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

In this work, we compared the WL driving schemes in 512 Gb planar NAND with 32 KB page size. In the conventional WL driving scheme, the rising time of the selected WL voltage is very large because of the large coupling capacitance between the selected and unselected WLs. The WL under-driving scheme (WLUDS) reduces the effect of coupling capacitance by using the 2-phase control of unselected WL voltage. However, when WLUDS is used, the relationship between the rising time and overshoot of the selected WL voltage should be considered in order to achieve the small rising time Therefore, we proposes a novel implementation method for WLUDS that controls the under-driving voltage and under-driving timing by using the decremental step voltage and incremental step time (DSVIST) to enhance the rising time considering the overshoot constraint. The HSPICE simulation using the 0.25-μm PTM model with the parasitic RC in 32 KB page size shows that the rising time in the proposed WLUDS with DSVIST is improved to 988 μs compared to 1206 μs in the conventional WL driving scheme.

Original languageEnglish
Title of host publicationISCAS 2016 - IEEE International Symposium on Circuits and Systems
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1022-1025
Number of pages4
Volume2016-July
ISBN (Electronic)9781479953400
DOIs
Publication statusPublished - 2016 Jul 29
Event2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016 - Montreal, Canada
Duration: 2016 May 222016 May 25

Other

Other2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016
CountryCanada
CityMontreal
Period16/5/2216/5/25

Fingerprint

Flash memory
Electric potential
Capacitance
Pulse time modulation
Phase control

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

Ko, J., Yang, Y., Jung, S., Kim, J., Lee, C. A., Min, Y. S., ... Kim, M. (2016). WL under-driving scheme with decremental step voltage and incremental step time for high-capacity NAND flash memory. In ISCAS 2016 - IEEE International Symposium on Circuits and Systems (Vol. 2016-July, pp. 1022-1025). [7527417] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS.2016.7527417
Ko, Junyoung ; Yang, Younghwi ; Jung, Seongook ; Kim, Jisu ; Lee, Cheon An ; Min, Young Sun ; Chun, Jinyoung ; Kim, Moosung. / WL under-driving scheme with decremental step voltage and incremental step time for high-capacity NAND flash memory. ISCAS 2016 - IEEE International Symposium on Circuits and Systems. Vol. 2016-July Institute of Electrical and Electronics Engineers Inc., 2016. pp. 1022-1025
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Ko, J, Yang, Y, Jung, S, Kim, J, Lee, CA, Min, YS, Chun, J & Kim, M 2016, WL under-driving scheme with decremental step voltage and incremental step time for high-capacity NAND flash memory. in ISCAS 2016 - IEEE International Symposium on Circuits and Systems. vol. 2016-July, 7527417, Institute of Electrical and Electronics Engineers Inc., pp. 1022-1025, 2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016, Montreal, Canada, 16/5/22. https://doi.org/10.1109/ISCAS.2016.7527417

WL under-driving scheme with decremental step voltage and incremental step time for high-capacity NAND flash memory. / Ko, Junyoung; Yang, Younghwi; Jung, Seongook; Kim, Jisu; Lee, Cheon An; Min, Young Sun; Chun, Jinyoung; Kim, Moosung.

ISCAS 2016 - IEEE International Symposium on Circuits and Systems. Vol. 2016-July Institute of Electrical and Electronics Engineers Inc., 2016. p. 1022-1025 7527417.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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N2 - In this work, we compared the WL driving schemes in 512 Gb planar NAND with 32 KB page size. In the conventional WL driving scheme, the rising time of the selected WL voltage is very large because of the large coupling capacitance between the selected and unselected WLs. The WL under-driving scheme (WLUDS) reduces the effect of coupling capacitance by using the 2-phase control of unselected WL voltage. However, when WLUDS is used, the relationship between the rising time and overshoot of the selected WL voltage should be considered in order to achieve the small rising time Therefore, we proposes a novel implementation method for WLUDS that controls the under-driving voltage and under-driving timing by using the decremental step voltage and incremental step time (DSVIST) to enhance the rising time considering the overshoot constraint. The HSPICE simulation using the 0.25-μm PTM model with the parasitic RC in 32 KB page size shows that the rising time in the proposed WLUDS with DSVIST is improved to 988 μs compared to 1206 μs in the conventional WL driving scheme.

AB - In this work, we compared the WL driving schemes in 512 Gb planar NAND with 32 KB page size. In the conventional WL driving scheme, the rising time of the selected WL voltage is very large because of the large coupling capacitance between the selected and unselected WLs. The WL under-driving scheme (WLUDS) reduces the effect of coupling capacitance by using the 2-phase control of unselected WL voltage. However, when WLUDS is used, the relationship between the rising time and overshoot of the selected WL voltage should be considered in order to achieve the small rising time Therefore, we proposes a novel implementation method for WLUDS that controls the under-driving voltage and under-driving timing by using the decremental step voltage and incremental step time (DSVIST) to enhance the rising time considering the overshoot constraint. The HSPICE simulation using the 0.25-μm PTM model with the parasitic RC in 32 KB page size shows that the rising time in the proposed WLUDS with DSVIST is improved to 988 μs compared to 1206 μs in the conventional WL driving scheme.

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Ko J, Yang Y, Jung S, Kim J, Lee CA, Min YS et al. WL under-driving scheme with decremental step voltage and incremental step time for high-capacity NAND flash memory. In ISCAS 2016 - IEEE International Symposium on Circuits and Systems. Vol. 2016-July. Institute of Electrical and Electronics Engineers Inc. 2016. p. 1022-1025. 7527417 https://doi.org/10.1109/ISCAS.2016.7527417