Abstract
Optimal thread-to-core mapping is a critical issue for performance improvement in a heterogeneous multi-core processor that consists of out-of-order cores and in-order cores. Through the scheduling, threads with heavy workloads can be executed in an out-of-order core, whereas other threads can be concurrently executed in in-order cores. In addition, a core speed variation is deemed a factor to improve the performance; therefore, a scheduler has to handle the heterogeneity to derive optimal speedup. In this paper, we propose the workload aware and estimation-based dynamic thread scheduling for a heterogeneous multi-core. The scheduler profiles the workload of threads and classifies the threads as sequential or parallel threads and detects critical sections that are the bottleneck of the program. Based on the profiled information, the scheduler estimates the expected performance of each core. Core monitoring process measures the speed variation of each core concurrently. Using the information of threads and cores, the scheduler allocates the thread to the appropriate processor core dynamically.
| Original language | English |
|---|---|
| Title of host publication | ISCE 2014 - 18th IEEE International Symposium on Consumer Electronics |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| ISBN (Print) | 9781479945924 |
| DOIs | |
| Publication status | Published - 2014 Jan 1 |
| Event | 18th IEEE International Symposium on Consumer Electronics, ISCE 2014 - Jeju, Korea, Republic of Duration: 2014 Jun 22 → 2014 Jun 25 |
Other
| Other | 18th IEEE International Symposium on Consumer Electronics, ISCE 2014 |
|---|---|
| Country | Korea, Republic of |
| City | Jeju |
| Period | 14/6/22 → 14/6/25 |
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All Science Journal Classification (ASJC) codes
- Engineering(all)
Cite this
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Workload and variation aware thread scheduling for heterogeneous multi-processor. / Lee, Seungwon; Ro, Won Woo.
ISCE 2014 - 18th IEEE International Symposium on Consumer Electronics. Institute of Electrical and Electronics Engineers Inc., 2014. 6884389.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
TY - GEN
T1 - Workload and variation aware thread scheduling for heterogeneous multi-processor
AU - Lee, Seungwon
AU - Ro, Won Woo
PY - 2014/1/1
Y1 - 2014/1/1
N2 - Optimal thread-to-core mapping is a critical issue for performance improvement in a heterogeneous multi-core processor that consists of out-of-order cores and in-order cores. Through the scheduling, threads with heavy workloads can be executed in an out-of-order core, whereas other threads can be concurrently executed in in-order cores. In addition, a core speed variation is deemed a factor to improve the performance; therefore, a scheduler has to handle the heterogeneity to derive optimal speedup. In this paper, we propose the workload aware and estimation-based dynamic thread scheduling for a heterogeneous multi-core. The scheduler profiles the workload of threads and classifies the threads as sequential or parallel threads and detects critical sections that are the bottleneck of the program. Based on the profiled information, the scheduler estimates the expected performance of each core. Core monitoring process measures the speed variation of each core concurrently. Using the information of threads and cores, the scheduler allocates the thread to the appropriate processor core dynamically.
AB - Optimal thread-to-core mapping is a critical issue for performance improvement in a heterogeneous multi-core processor that consists of out-of-order cores and in-order cores. Through the scheduling, threads with heavy workloads can be executed in an out-of-order core, whereas other threads can be concurrently executed in in-order cores. In addition, a core speed variation is deemed a factor to improve the performance; therefore, a scheduler has to handle the heterogeneity to derive optimal speedup. In this paper, we propose the workload aware and estimation-based dynamic thread scheduling for a heterogeneous multi-core. The scheduler profiles the workload of threads and classifies the threads as sequential or parallel threads and detects critical sections that are the bottleneck of the program. Based on the profiled information, the scheduler estimates the expected performance of each core. Core monitoring process measures the speed variation of each core concurrently. Using the information of threads and cores, the scheduler allocates the thread to the appropriate processor core dynamically.
UR - http://www.scopus.com/inward/record.url?scp=84907316999&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84907316999&partnerID=8YFLogxK
U2 - 10.1109/ISCE.2014.6884389
DO - 10.1109/ISCE.2014.6884389
M3 - Conference contribution
SN - 9781479945924
BT - ISCE 2014 - 18th IEEE International Symposium on Consumer Electronics
PB - Institute of Electrical and Electronics Engineers Inc.
ER -