Worst case execution time analysis for synthesized hardware

Jun Hee Yoo, Xingguang Feng, Kiyoung Choi, Eui Young Chung, Kyu Myung Choi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

We propose a hardware performance estimation flow for fast design space exploration, based on worst-case execution time analysis algorithms for software analysis. Test cases on some real-world applications show that our flow provides a tight upper bound of the execution time, and many useful hints to the designer.

Original languageEnglish
Title of host publicationProceedings of the ASP-DAC 2006
Subtitle of host publicationAsia and South Pacific Design Automation Conference 2006
Pages905-910
Number of pages6
Publication statusPublished - 2006 Sep 19
EventASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006 - Yokohama, Japan
Duration: 2006 Jan 242006 Jan 27

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Volume2006

Other

OtherASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006
CountryJapan
CityYokohama
Period06/1/2406/1/27

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All Science Journal Classification (ASJC) codes

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

Cite this

Yoo, J. H., Feng, X., Choi, K., Chung, E. Y., & Choi, K. M. (2006). Worst case execution time analysis for synthesized hardware. In Proceedings of the ASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006 (pp. 905-910). [1594801] (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; Vol. 2006).