Yield enhancement techniques for 3D memories by redundancy sharing among all layers

Joohwan Lee, Kihyun Park, Sungho Kang

Research output: Contribution to journalArticle

5 Citations (Scopus)

Abstract

Three-dimensional (3D) memories using through-silicon vias (TSVs) will likely be the first commercial applications of 3D integrated circuit technology. A 3D memory yield can be enhanced by vertical redundancy sharing strategies. The methods used to select memory dies to form 3D memories have a great effect on the 3D memory yield. Since previous die-selection methods share redundancies only between neighboring memory dies, the opportunity to achieve significant yield enhancement is limited. In this paper, a novel die-selection method is proposed for multi-layer 3D memories that shares redundancies among all of the memory dies by using additional TSVs. The proposed method uses three selection conditions to form a good multi-layer 3D memory. Furthermore, the proposed method considers memory fault characteristics, newly detected faults after bonding, and multiple memory blocks in each memory die. Simulation results show that the proposed method can significantly improve the multilayer 3D memory yield in a variety of situations. The TSV overhead for the proposed method is almost the same as that for the previous methods.

Original languageEnglish
Pages (from-to)388-398
Number of pages11
JournalETRI Journal
Volume34
Issue number3
DOIs
Publication statusPublished - 2012 Jun 1

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Redundancy
Data storage equipment
Silicon
Multilayers

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Computer Science(all)
  • Electrical and Electronic Engineering

Cite this

Lee, Joohwan ; Park, Kihyun ; Kang, Sungho. / Yield enhancement techniques for 3D memories by redundancy sharing among all layers. In: ETRI Journal. 2012 ; Vol. 34, No. 3. pp. 388-398.
@article{268ebd54451649df838c755b3fe8c2eb,
title = "Yield enhancement techniques for 3D memories by redundancy sharing among all layers",
abstract = "Three-dimensional (3D) memories using through-silicon vias (TSVs) will likely be the first commercial applications of 3D integrated circuit technology. A 3D memory yield can be enhanced by vertical redundancy sharing strategies. The methods used to select memory dies to form 3D memories have a great effect on the 3D memory yield. Since previous die-selection methods share redundancies only between neighboring memory dies, the opportunity to achieve significant yield enhancement is limited. In this paper, a novel die-selection method is proposed for multi-layer 3D memories that shares redundancies among all of the memory dies by using additional TSVs. The proposed method uses three selection conditions to form a good multi-layer 3D memory. Furthermore, the proposed method considers memory fault characteristics, newly detected faults after bonding, and multiple memory blocks in each memory die. Simulation results show that the proposed method can significantly improve the multilayer 3D memory yield in a variety of situations. The TSV overhead for the proposed method is almost the same as that for the previous methods.",
author = "Joohwan Lee and Kihyun Park and Sungho Kang",
year = "2012",
month = "6",
day = "1",
doi = "10.4218/etrij.12.0111.0643",
language = "English",
volume = "34",
pages = "388--398",
journal = "ETRI Journal",
issn = "1225-6463",
publisher = "ETRI",
number = "3",

}

Yield enhancement techniques for 3D memories by redundancy sharing among all layers. / Lee, Joohwan; Park, Kihyun; Kang, Sungho.

In: ETRI Journal, Vol. 34, No. 3, 01.06.2012, p. 388-398.

Research output: Contribution to journalArticle

TY - JOUR

T1 - Yield enhancement techniques for 3D memories by redundancy sharing among all layers

AU - Lee, Joohwan

AU - Park, Kihyun

AU - Kang, Sungho

PY - 2012/6/1

Y1 - 2012/6/1

N2 - Three-dimensional (3D) memories using through-silicon vias (TSVs) will likely be the first commercial applications of 3D integrated circuit technology. A 3D memory yield can be enhanced by vertical redundancy sharing strategies. The methods used to select memory dies to form 3D memories have a great effect on the 3D memory yield. Since previous die-selection methods share redundancies only between neighboring memory dies, the opportunity to achieve significant yield enhancement is limited. In this paper, a novel die-selection method is proposed for multi-layer 3D memories that shares redundancies among all of the memory dies by using additional TSVs. The proposed method uses three selection conditions to form a good multi-layer 3D memory. Furthermore, the proposed method considers memory fault characteristics, newly detected faults after bonding, and multiple memory blocks in each memory die. Simulation results show that the proposed method can significantly improve the multilayer 3D memory yield in a variety of situations. The TSV overhead for the proposed method is almost the same as that for the previous methods.

AB - Three-dimensional (3D) memories using through-silicon vias (TSVs) will likely be the first commercial applications of 3D integrated circuit technology. A 3D memory yield can be enhanced by vertical redundancy sharing strategies. The methods used to select memory dies to form 3D memories have a great effect on the 3D memory yield. Since previous die-selection methods share redundancies only between neighboring memory dies, the opportunity to achieve significant yield enhancement is limited. In this paper, a novel die-selection method is proposed for multi-layer 3D memories that shares redundancies among all of the memory dies by using additional TSVs. The proposed method uses three selection conditions to form a good multi-layer 3D memory. Furthermore, the proposed method considers memory fault characteristics, newly detected faults after bonding, and multiple memory blocks in each memory die. Simulation results show that the proposed method can significantly improve the multilayer 3D memory yield in a variety of situations. The TSV overhead for the proposed method is almost the same as that for the previous methods.

UR - http://www.scopus.com/inward/record.url?scp=84863324137&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84863324137&partnerID=8YFLogxK

U2 - 10.4218/etrij.12.0111.0643

DO - 10.4218/etrij.12.0111.0643

M3 - Article

AN - SCOPUS:84863324137

VL - 34

SP - 388

EP - 398

JO - ETRI Journal

JF - ETRI Journal

SN - 1225-6463

IS - 3

ER -